W25Q64JVSSIQ

1. DESCRIPTIONS

The W25Q64JVSSIQ (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.

The W25Q64JVSSIQ array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64JVSSIQ has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)

The W25Q64JVSSIQ supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. SPI clock frequencies of W25Q64JVSSIQ of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories.

Additionally, the device supports JEDEC standard manufacturer and device ID, and a 64-bit Unique Serial Number and three 256-bytes Security Registers.

2. FEATURES

    1. New Family of SpiFlash Memories

         – W25Q64JV: 64M-bit / 8M-byte

         – Standard SPI: CLK, /CS, DI, DO

         – Dual SPI: CLK, /CS, IO0, IO1

         – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

         – Software & Hardware Reset(1)

    2. Highest Performance Serial Flash

         – 133MHz Single, Dual/Quad SPI clocks

         – 266/532MHz equivalent Dual/Quad SPI

         – Min. 100K Program-Erase cycles per sector

         – More than 20-year data retention

    3. Low Power, Wide Temperature Range

         – Single 2.7 to 3.6V supply

         – <1µA Power-down (typ.)

         – -40°C to +85°C operating range

         – -40°C to +105°C operating range

    4. Flexible Architecture with 4KB sectors

         – Uniform Sector/Block Erase (4K/32K/64K-Byte)

         – Program 1 to 256 byte per programmable page

         – Erase/Program Suspend & Resume

    5. Advanced Security Features

        – Software and Hardware Write-Protect

        – Special OTP protection

        – Top/Bottom, Complement array protection

        – Individual Block/Sector array protection

        – 64-Bit Unique ID for each device

        – Discoverable Parameters (SFDP) Register

        – 3X256-Bytes Security Registers

        – Volatile & Non-volatile Status Register Bits

    6. Space Efficient Packaging

        – 8-pin SOIC 208-mil

        – 8-pad WSON 6x5-mm/8x6-mm

        – 16-pin SOIC 300-mil

        – 8-pad XSON 4x4-mm

        – 24-ball TFBGA 8x6-mm (6x4 ball array)

        – 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)

        – 12-ball WLCSP 

        – Contact Winbond for KGD and other options

3. Pin Configuration SOIC 208-mil

4. Pin Description SOIC 208-mil, WSON 6x5-mm/ 8x6-mm, XSON 4x4-mm

5. FUNCTIONAL DESCRIPTIONS

    1. Standard SPI Instructions

    2. Dual SPI Instructions 

    3. Quad SPI Instructions

    4. Software Reset & Hardware /RESET pin

Upon power-up or at power-down, the W25Q64JV will maintain a reset condition while VCC is below the threshold value of VWI, While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCCmin level and tVSL time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control.