XC6SLX150T-3FGG676I

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1. Description

The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.

2. Feature summary

    1. Spartan-6 Family:

        - Spartan-6 LX FPGA: Logic optimized

        - Spartan-6 LXT FPGA: High-speed serial connectivity

    2. Designed for low cost

        - Multiple efficient integrated blocks

        - Optimized selection of I/O standards

        - Staggered pads

        - High-volume plastic wire-bonded packages

    3. Low static and dynamic power

        - 45 nm process optimized for cost and low power

        - Hibernate power-down mode for zero power

        - Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement

        - Lower-power 1.0V core voltage (LX FPGAs, -1L only)

        - High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)

    4. Multi-voltage, multi-standard SelectIO™ interface banks

        - Up to 1,080 Mb/s data transfer rate per differential I/O

        - Selectable output drive, up to 24 mA per pin

        - 3.3V to 1.2V I/O standards and protocols

        - Low-cost HSTL and SSTL memory interfaces

        - Hot swap compliance

        - Adjustable I/O slew rates to improve signal integrity

    5. High-speed GTP serial transceivers in the LXT FPGAs

        - Up to 3.2 Gb/s

        - High-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI

    6. Integrated Endpoint block for PCI Express designs (LXT)

    7. Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.

    8. Efficient DSP48A1 slices

        - High-performance arithmetic and signal processing

        - Fast 18 x 18 multiplier and 48-bit accumulator

        - Pipelining and cascading capability

        - Pre-adder to assist filter applications

    9. Integrated Memory Controller blocks

        - DDR, DDR2, DDR3, and LPDDR support

        - Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)

        - Multi-port bus structure with independent FIFO to reduce design timing issues

  10. Abundant logic resources with increased logic capacity

        - Optional shift register or distributed RAM support

        - Efficient 6-input LUTs improve performance and minimize power

        - LUT with dual flip-flops for pipeline centric applications

  11. Block RAM with a wide range of granularity

        - Fast block RAM with byte write enable

        - 18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs

  12. Clock Management Tile (CMT) for enhanced performance

        - Low noise, flexible clocking

        - Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion

        - Phase-Locked Loops (PLLs) for low-jitter clocking

        - Frequency synthesis with simultaneous multiplication, division, and phase shifting

        - Sixteen low-skew global clock networks

 13. Simplified configuration, supports low-cost standards

       - 2-pin auto-detect configuration

       - Broad third-party SPI (up to x4) and NOR flash support

       - Feature rich Xilinx Platform Flash with JTAG

       - MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection

  14. Enhanced security for design protection

        - Unique Device DNA identifier for design authentication

        - AES bitstream encryption in the larger devices

  15. Faster embedded processing with enhanced, low cost, MicroBlaze™ soft processor

  16. Industry-leading IP and reference designs

3. Configuration

Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 3 Mb and 33 Mb depending on device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available. Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal, or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations, master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and 16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan protocols to load bit-serial configuration data. The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration process typically executes the following sequence:

    1. Detects power-up (power-on reset) or PROGRAM_B when Low.

    2. Clears the whole configuration memory.

    3. Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.

    4. Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.

    5. Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.

The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial flash PROM. The Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel NOR flash. Note that BPI configuration is not supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using Spartan-6 FPGAs in TQG144 and CPG196 packages. Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in a single configuration source. The FPGA application controls which configuration to load next and when to load it. Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier that is useful for tracking purposes, anticloning designs, or IP protection. In the largest devices, bitstreams can be copy protected using AES encryption.

4. I/O Electrical Characteristics

Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards VCCO or Low towards ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors, adjustable output drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO Resources User Guide for more details on available options for each I/O standard.