XCS10XL-4TQ144C

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1. Description

Spartan® and Spartan-XL FPGA series are Mass production FPGA solutions, can provide all The key requirement for ASIC replacement (up to 40,000 gates).

These requirements include high performance, on-chip Large amounts of RAM, core solutions and prices This method is equivalent to mask-programmed ASIC devices in many cases.

By streamlining the feature set of the Spartan series,Advanced process technology and focus on total cost Management, the Spartan series provides key functions Required by ASIC and other large number of logic users Avoid the initial cost of traditional ASIC, long development cycle and inherent risks. The Spartan and Spartan-XL series in the Spartan series have ten members。

2. General overview

Spartan series FPGA adopts the conventional, flexible and programmable architecture of configurable logic block (CLB), and is interconnected through a powerful hierarchical structure General routing resources (routing channels), surrounded by programmable input/output ranges Blocks (IOB), they have enough space for routing resources to accommodate the most complex interconnection patterns. Customize the device by loading the configuration data into the internal static storage unit. Reprogramming is unlimited. The values stored in these storage units determine the logical functions and interconnections implemented in the FPGA. FPGA can actively read its configuration data PROM (master serial mode) from an external serial, or configuration data can be written into FPGA serial mode from an external device (slave station). Spartan series FPGAs can be used where hardware is needed to adapt to different user applications. FPGAs are ideal for shortening design and development cycles, as well as providing a cost-effective productivity solution for over 50,000 systems per month.

3. Spartan / Spartan-XL FPGA features

Note: The Spartan series devices described in this article include 5V Spartan series and 3.3V Spartan-XL series. For more senior members of the Spartan series, please see PDF.

   1. The first ASIC that can be mass produced through on-chip RAM to replace FPGA

   2. Density up to 1862 logic units or 40,000 system gates

   3. Simplified feature set based on XC4000 architecture

   4. System performance exceeds 80 MHz

   5. Provide a wide range of AllianceCORE and LogiCORE™ predefined solutions

   6. Unlimited reprogrammability

   7. low cost

4. System level functions

   1. Provide 5V and 3.3V versions

   2. On-chip SelectRAM™ memory

   3. Compliant with PCI

   4. Complete readback function for program verification And observability of internal nodes

   5. Dedicated high-speed carry logic

   6. Internal tri-state bus function

   7. Eight global low-bias clock or signal networks

   8. Compatible with IEEE 1149.1 boundary scan logic

   9. Low-cost plastic packaging of various densities

 10. Package compatibility in general packages

5. Powerful XilinxISE®Classics comprehensive support development system

1. Fully automatic mapping, placement and routing

6. Additional Spartan-XL Family Features

   1. 3.3V power supply, can withstand 5V I/O, achieve low power consumption

   2. Power down input

   3. Higher performance

   4. Faster carry logic

   5. More flexible high-speed clock network

   6. Configurable latch function in logic block

   7. Input fast capture latch

   8. Optional MUX or 2-input function generator on the output

   9. 12 mA or 24 mA output driver

 10. Compliant with 5V and 3.3V PCI

 11. Enhanced boundary scan

 12. Quick mode configuration

7. CLB can implement any of the following functions:

   1. Any function, up to four variables, plus the second A function of up to four unrelated variables, plus any third variable Function of up to three unrelated variables

       Note: When generating three separate functions, one of them Function output must be captured in internal trigger CLB. Only two unregistered function generator outputs Available from CLB.

   2. Any single function of five variables

   3. Any function of the four variables and some Six variable functions

   4. Some functions contain up to 9 variables.

Implementing a wide range of functions in a single block can reduce both The number of blocks required and the delay in the signal Path while increasing capacity and speed.

CLB function generator has remarkable versatility Improve system speed. In addition, design software The tool can handle each function generator independently.

This flexibility improves battery usage.