XCS20-4PQ208C

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1. Describe

Spartan series FPGAs are implemented using traditional, flexible, and programmable configurable logic architecture Blocks (CLB), interconnected through a strong hierarchy Multi-function routing resource (routing channel), programmable input/output around Block (IOB), routing resources adapt to the most complex interconnection patterns. Customize the device by loading configuration data Enter the internal static storage unit. Can be reprogrammed indefinitely. Stored in these values The memory cell determines the logic functions and interconnections implemented in the FPGA. FPGA can Actively read its configuration data from the external serial port PROM (master serial mode), or configuration data can be Write to FPGA serial mode from external device (slave device). Spartan series FPGAs can be used for hardware must Adapt to different user applications. FPGA is the ideal choice Shorten the design and development cycle, Provide cost-effective solutions to increase productivity More than 50,000 systems per month. Spartan and Spartan-XL devices provide system clock Over 80 MHz rate and internal performance More than 150 MHz. In addition to the traditional benefits High-capacity programmable logic solution, Spartan Series FPGAs also provide on-chip edge-triggered single port And dual-port RAM, clock enable all flip-flops, fast carry Logic and many other functions. The Spartan/XL family took advantage of the very successful The XC4000 architecture has many functions and benefit. Technological progress has been derived Derived from XC4000XLA process development.

2. Feature

    1. The first ASIC to replace FPGA for mass production Production with on-chip RAM

    2. Density up to 1862 logic cells or 40,000 system gates

    3. Streamlined feature set based on XC4000 architecture

    4. System performance over 80 MHz

    5. Extensive AllianceCORE and LogiCORE™ Pre-defined solutions available

    6. Unlimited reprogrammability

    7. low cost

    8. System level functions

        - Available in 5V and 3.3V versions

        - On-chip SelectRAM™ memory

        - Fully compliant with PCI standards

        - Full readback function for program verification And internal node observability

        - Dedicated high-speed carry logic

        - Internal tri-state bus capability

        - Eight global low-skew clock or signal networks

        - IEEE 1149.1 compatible boundary scan logic

        - Low-cost plastic packaging of various densities

        - Package compatibility in general packages

    9. Fully supported by the powerful Xilinx ISE® Classics development system

        - Fully automatic mapping, placement and routing

3. Other Spartan-XL series features

    1. 3.3V low-power power supply with 5V tolerant I/O

    2. Power-down input

    3. Higher performance

    4. Faster carry logic

    5. More flexible high-speed clock network

    6. Configurable latching capabilities in logic blocks

    7. Input fast capture latch

    8. Optional MUX or 2-input function generator on the output

    9. 12 mA or 24 mA output drive

  10. 5V and 3.3V PCI compatible

  11. Enhanced boundary scan

  12. Quick mode configuration

4. Function generator

Two 16 x 1 memory lookup tables (F-LUT and G-LUT) are Used to implement 4-input function generators, each generator provides up to four independent input signals (F1 to F4 or G1 to G4) of any Boolean function unlimited logic implementation. Using a memory lookup table, the propagation delay has nothing to do with the implemented function. The third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of the inputs are controlled by a programmable multiplexer. These inputs can come from F-LUT or G-LUT output or from CLB input. The third input always comes from the CLB input. Therefore, CLB can implement certain functions with up to nine inputs, such as parity checking. The three LUTs in the CLB can also be combined to perform arbitrarily defined five-input Boolean functions.