Allicdata Part #: | LAN91C113-NS-ND |
Manufacturer Part#: |
LAN91C113-NS |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Microchip Technology |
Short Description: | IC ETHERNET CTLR MAC PHY 128QFP |
More Detail: | Ethernet Controller 10/100 Base-T/TX PHY Parallel ... |
DataSheet: | LAN91C113-NS Datasheet/PDF |
Quantity: | 132 |
Series: | -- |
Packaging: | Tray |
Part Status: | Active |
Protocol: | Ethernet |
Function: | Controller |
Interface: | Parallel |
Standards: | 10/100 Base-T/TX PHY |
Voltage - Supply: | 3.3V |
Current - Supply: | 100mA |
Operating Temperature: | 0°C ~ 85°C |
Package / Case: | 128-BQFP |
Supplier Device Package: | 128-QFP |
Base Part Number: | LAN91C113 |
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The LAN91C113-NS is a single chip Ethernet controller, which is a popular choice for many interface - controllers applications. It is based on the National Semiconductor\'s LAN91C110 Ethernet controller. It integrates a 16-bit low power, high performance micro-controller core and a variety of communication, memory, and debugging features into a single chip.
The LAN91C11-NS allows designers to build systems with robust Ethernet communication capabilities for a wide range of applications. It is designed for fast and easy integration into network-enabled systems. It supports 10, 100 and 1000 Mbps Ethernet connections at full duplex wire speeds.
The chip supports a variety of functions including packet segmentation and reassembly, flow control and error checking, media independent interface support, 33-bit address recognition and support for multicast and broadcast functions.
The LAN91C11-NS is designed for low power consumption, high performance, and scalable design. The chip supports a variety of peripheral interfaces, including External Bus Interface, Universal Affinity Bus (UAB), Serial Peripheral Interface (SPI), and Advanced Microcontroller Bus Architecture (AMBA). It also includes boot ROM, EEPROM, and SRAM.
The chip features features an integrated energy efficient hardware-based packet processing subsystem and a hardware-based packet reception/transmission subsystem. The packet processing subsystem is designed for efficient packet transmission and processing, enabling fast and secure Ethernet connections. The packet transmission/reception subsystem is designed for speedy data movement between the LAN91C11-NS and the rest of the system.
The LAN91C11-NS can be programmed via a range of programming languages. These languages include ANSI C and Scheme, as well as assembly languages, which are specifically tailored for the chip. The device includes a debug mode that allows users to debug their code and reduce development time. The device also includes a built-in on-chip debugging tool that is compatible with the GNU debugger. The device supports a wide range of operating systems, including Windows, Linux, FreeBSD, and MAC.
The working principle of the LAN91C11-NS is simple. The chip sends data over an Ethernet connection and receives information from other nodes on the same network. The chip performs a variety of functions including packet segmentation, flow control and error checking, to ensure that data is received and sent out over the network in a secure and reliable manner.
The LAN91C11-NS is a powerful and efficient solution for many interface- controllers. It features low power consumption, high performance, scalable design, and a variety of communication, memory, and debugging features. It is easy to program via a range of programming languages and supports a variety of operating systems. The chip sends and receives data reliably over an Ethernet connection and is an ideal solution for embedded systems.
The specific data is subject to PDF, and the above content is for reference
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