LAN9352I/ML

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LAN9352I/ML is a dual-port, high-performance, fully-integrated Ethernet switch compliant with the IEEE 802.3 standard. This device is designed for use in embedded systems where both versatility and high performance are required. It provides two 10/100 Mbps Ethernet ports, each with an independent and fully programmable MAC layer. These ports can be configured in various combinations including independent ports or mirrored pair and a dedicated MII or RMII link providing a shared connection to the host processor or an external transceiver. The device also supports Quality-of-Service operations and configurable packet buffer sizes.

The LAN9352I/ML is configured as an interface controller, enabling access to Ethernet networks. This device provides the control necessary to maintain data integrity and control bandwidth. The Management Data Input/Output (MDIO) management interface is a generic data interface to the PHY layer, allowing access to registers, status information, and diagnostics. It supports an Integrated ARM7TDMI-S 32-bit processor and Ethernet MACs, plus seven integrated 8-bit DMA controllers for data packet management. It also offers per packet accountability for packet size and data content during transmission and reception. This device offers an advanced packet forwarding architecture that allows for efficient data transfer between the ports.

The LAN9352I/ML features an optional multiple in-line memory module interface that is capable of providing high-speed access to external memory. This interface is compliant with the industry standard DDR2 or DDR3 protocols, and is optimized for read and write operations. This interface can be used to store MAC address tables, packet filters, and other data that needs to be read or written quickly.

The device offers an integrated buffer manager for links between the two Ethernet ports and the host system. This buffer manager takes full advantage of the multiple DMA channels, allowing the CPU to switch between links quickly. The allocation of bandwidth amongst multiple link groups is also supported, allowing users to improve traffic flows between links. This supports both a multi-hop packet forwarding mode and a single-hop packet forwarding mode, allowing users to improve performance of data transfers.

The Ethernet controller in the LAN9352I/ML is also compliant with the IEEE 802.1p protocol. This protocol is used to prioritize data frames based on their traffic types, allowing users to improve overall performance of Ethernet networks. This protocol enables faster data transfer of time-sensitive frames such as real-time audio and video applications. Furthermore, it supports 802.1Q VLAN tagging, allowing users to isolate traffic types within a network.

The LAN9352I/ML also features an on-chip 32-bit eXtreme Low Power sleep mode timer. This timer allows the device to enter a low-power state for a predetermined period of time based on user configuration. The device can then be periodically awaken to handle received data frames and send out frames. This makes the device ideal for applications where power consumption is a primary concern.

The LAN9352I/ML is an ideal Ethernet controller for embedded systems. Its versatile architecture and user configurable features allow it to handle different networking requirements, providing maximum control and performance. Its on-chip buffer manager, IEEE 802.1Q VLAN support, and integrated eXtreme Low Power sleep mode timer make it optimal for power intensive applications. With its flexibility and performance, it is an ideal choice for embedded devices that require Ethernet connectivity.

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