Trigger

l  Trigger

Timing logic circuit  usually has feedback or memory and memory cell, and the output signal is not only related to the input signal at that time, and it has to do with the previous state of output. In order to distinguish the difference between the same terminal signal before and after the change, it is generally used to distinguish the upper corner of the mark, the upper corner of the original value of the standard n, n + 1 denotes the new value after change, such as Q, which represents the original state of Q, which is called the present state; q  denotes the new state of Q, which is called substate.

The trigger is the basic unit of the sequential logic circuit, and the trigger itself has a very wide range of applications. There is usually feedback inside the trigger, which can play a role of storage and memory.

l  Basic SR latch

 SR latches are sometimes referred to as RS flip-flops. SR latch is divided into basic SR latch and gated SR latch. The basic SR latch is the basic unit of various latches and flip-flops, and is also commonly used in the debounce circuit of the button or switch; gated SR latches are rarely used alone and generally appear in the internal structure of the integrated trigger. The basic SR latch consists of two circuit structures, either a non-gate SR latch and a non-gate SR latch. They all have feedback, and achieve the function of memory through the self-sustaining function of feedback.

l   The state transition diagram and the use of notes

 ( 1 ) state transition diagram is a common tool in sequential logic circuit, and write the state in the circle, the arrow represents the direction of the state transition, and the conversion condition is written next to the arrow.

( 2 ) Note that if there are some special reasons, it will cause the SR latch to be valid at the same time ( against the constraints ), the output is deterministic and has Q = Q; however, when the separation is effective, if the input signal of the two inputs is not valid at the same time, the delay time of the gate circuit is different, the output may be a state, or a 0 state.

For an actual SR latch that is connected, the output is a defined 0 state or a defined 1 state, since the delay duration of the two integrated circuits is determined, that is, the output of the actual SR latch is determined, but requires actual testing.

Therefore, when replacing an integrated circuit or producing a plurality of products, it is not possible to guarantee what is the output state of the integrated circuit, and when the product is actually produced, the consistency of all products must be guaranteed, so this problem must be taken into account when designing circuits with SR latches, if this cannot be tolerated, you need to select other types of latches or triggers.

This article is from Allicdata Electronics Limited.