What are the basic structure of FPGA?
The basic components of FPGA are: programmable I\O unit, basic programmable logic unit, embedded RAM block, rich wiring resources, underlying embedded functional unit and embedded dedicated hard core.
1. Programmable I\O unit:
The programmable I\O unit can adapt to different electrical standards and physical characteristics through software.
2. Embedded RAM block:
The embedded RAM block of FPGA can be flexibly configured as single-port RAM (SPRAM, SinglePortRAM), dual-port RAM (DPRAM, DoublePortRAM), pseudo dual-port RAM (PseudoDPRAM), CAM (ContentAddressableMemory), FIFO (FirsTInputFirstOutput) and other common memory structures.
There is no dedicated ROM hardware resource in FPGA. The idea of realizing ROM is to assign initial value to RAM and keep the initial value.
CAM, the content address memory. The CAM memory contains an embedded comparison logic in each storage unit. The data written to the CAM will be compared with each data stored in the CAM and return the address of all internal data that is the same as the port.
In short, RAM is a storage unit that reads and writes data according to the address, and CAM returns an internal address that matches the port data.
The internal realization of RAM, ROM, CAM, FIFO and other storage structures in FPGA is based on the embedded RAM block, and automatically generates the corresponding glue logic (GlueLogic) to complete the control logic such as address and chip selection.
The common RAM block size of Xilinx is 4Kbit and 18Kbit. The commonly used RAM block size of LatTIce is 9Kbit. Altera's RAM block is the most flexible. Some high-end devices contain two RAM block structures at the same time, which are M9KRAM (9Kbit), M -144K (144Kbit).
In addition to RAM, FPGAs from Altera, Xilinx, and LatTIce can flexibly configure LUTs into storage structures such as RAM, ROM, and FIFO. This technology is called distributed RAM (Distributed RAM).
3. Basic programmable logic unit:
The basic programmable logic unit is the main body of FPGA programmable logic. FPGA is generally based on SRAM technology. The basic programmable logic unit is almost composed of look-up table (LUT, LookUpTable) and register (Register). The LUT inside the FPGA is generally 4 inputs, mainly to complete pure combinational logic functions. The internal register structure is quite flexible and can be configured as a flip-flop (FF, FlipFlop) with synchronous, asynchronous reset or set, clock enable, or as a latch (Latch). FPGA generally relies on registers to complete synchronous sequential logic design.
The classic configuration of a basic programmable logic unit is a register and a lookup table. However, the internal structures of registers and lookup tables of different manufacturers are different, and the combination mode of registers and lookup tables is also different.
(1) The programmable logic unit of Alerta is usually called LE (LogicElement, logic unit), which is composed of a Register and a LUT. Most Altera FPGAs combine 10 LEs together to form a larger logic function unit-Logic Array Block (LAB, LogicArrayBlock). In addition to LEs, LAB also contains the carry chain between LEs, LAB control signals, and local Wire and control resources such as interconnect line resources, LUT cascade chain, and register cascade chain.
(2) The programmable logic unit of Xilinx is called Slice, which is composed of upper and lower parts. Each part is composed of a Register and a LUT, which is called LC (LogicCell), and there is some common logic between the two LCs. Can complete the coordination and cascade between LC.
(3) Lattice's programmable logic unit is called PFU (ProgrammableFunctionUnit, Programmable Function Unit) and is composed of 8 LUTs and 8-9 Registers.
It is generally more accurate to use the number of registers and LUTs of the device to measure the size of the device.
4. Embedded functional units at the bottom
Highly versatile embedded function modules, such as PLL (PhaseLockedLoop), DLL (DelayLockedLoop), DSP and CPU.
Altera chip integrates PLL, Xilinx chip mainly integrates DLL, LatTIce's new FPGA also integrates PLL and DLL to meet different needs.
Altera chip PLL module is divided into enhanced PLL (EnhancedPLL) and fast PLL (FastPLL).
The module name of Xilinx chip DLL is CLKDLL, and the enhanced module of CLKDLL in high-end FPGA is DCM (Digital Clock Manager, digital clock management module).
5. Embedded special hard core
The versatility of the embedded dedicated hard core is relatively weak, and not all FPGA devices include a hard core.
There are also two camps within the FPGA: on the one hand, it is a FPGA with strong versatility, a wide range of target markets, and a moderate price; on the other hand, it is a FPGA with a strong target, a clear target market, and a higher price.
The wiring resources connect all the units inside the FPGA, and the length and process of the wiring determine the driving capability and transmission speed of the signal on the wiring. There are the following three wiring resources available.
(1) Global dedicated routing resources: used to complete the routing of the global clock and global reset\set in the device.
(2) Long-line resources: complete the wiring of some high-speed signals and some second global clock signals between device banks.
(3) Short-term resources: complete the logical interconnection and wiring between basic logic units.
(4) There are also various wiring resources and dedicated clock and reset control signal lines inside the basic logic unit.
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