What are the processes and precautions for typical FPGA development?
According to the experience of the FPGA technology cattle people over the years, the basic process of FPGA development and the basic introduction of the precautions, I hope to help beginners. As we all know, FPGA is a programmable chip, so the design method of FPGA includes hardware design and software design. The hardware includes FPGA chip circuits, memory, input and output interface circuits, and other devices. The software is the corresponding HDL program and embedded C program.
Since the current microelectronics technology has evolved to the SOC stage, the Integrated System stage, there has been a revolutionary change in the design philosophy of integrated circuits (ICs). SOC is a complex system that integrates the functions of a complete product on a single chip, including core processor, storage unit, hardware acceleration unit, and numerous external device interfaces. It has a long design cycle and high implementation cost. The design method must be the top-down software and hardware collaborative design from the system level to the functional module, achieving a seamless combination of software and hardware.
Such a large workload is clearly beyond the capabilities of a single engineer, so it needs to be implemented in a hierarchical, structured design approach. First, the chief designer divides the entire software development task into several operational modules, evaluates its interfaces and resources, compiles the corresponding behavior or structural model, and assigns it to the next layer of designers. This allows multiple designers to simultaneously design different modules in a hardware system and be responsible for the modules they design; then the upper layer designer performs functional verification on the lower modules.
The top-down design process begins with a system-level design and is divided into a number of secondary units, which are then divided into the basic units of the next level. Until then, until the basic module or IP core can be directly implemented, popular FPGA development tools provide hierarchical management, which can effectively sort out the intricate layers, and can easily view the source code of a certain level of modules to modify the error.
In engineering practice, there is also the problem of software compilation time. Because large-scale design contains multiple complex functional modules, its timing convergence and simulation verification complexity is very high. In order to meet the requirements of time series indicators, it is often necessary to repeatedly modify the source files, and then recompile the modified new version until the requirements are met. until.
There are two problems in this: First, software compilation takes up to several hours or even weeks, which is not tolerated by development; secondly, the results after recompilation and place and route are very different, and the timing will be met. The circuit is broken. Therefore, it is necessary to propose a software tool that effectively improves the design performance, inherits the existing results, and is convenient for team design. FPGA vendors are aware of this type of need and have developed software tools for logical locking and incremental design. For example, Xilinx's solution is PlanAhead.
Planahead allows high-level designers to partition the corresponding FPGA chip area for different modules, and allows the underlying designer to independently design, implement, and optimize in a given area, and then integrate the design after each module is correct. If an error occurs in the design integration, it can be modified separately without affecting other modules. Planahead combines structured design methods, team-based collaborative design methods, and reused inheritance design methods to effectively improve design efficiency and design cycle.
However, it can be seen from the description that the new design method has high requirements for the top designer of the system. In the early stage of design, they not only need to evaluate the resources consumed by each sub-module, but also need to give corresponding timing relationship; in the later stage of design, it needs to be revised according to the implementation of the underlying module.
The FPGA design flow is the process of developing FPGA chips using EDA development software and programming tools. The development process of a typical FPGA, including function definition/device selection, design input, function simulation, comprehensive optimization, post-synthesis simulation, implementation, post-route simulation, board-level simulation, and chip programming and debugging. The main steps.
Before the start of the FPGA design project, there must be a definition of the system function and the division of the module. In addition, according to the task requirements, such as the function and complexity of the system, the work speed and the resources, cost, and connection of the device itself can be laid. Weigh the sex and other aspects, choose the right design and the right device type. Generally, the top-down design method is adopted, the system is divided into several basic units, and then each basic unit is divided into the basic units of the next level, and this is continued until the EDA component library can be directly used.
Design input is the process of designing a system or circuit in some form of development software requirements and inputting it to an EDA tool. Commonly used methods are hardware description language (HDL) and schematic input methods. The schematic input method is the most direct way to describe. It is widely used in the early development of programmable chips. It will transfer the required devices from the component library and draw the schematic. Although intuitive and easy to simulate, this method is inefficient and difficult to maintain, which is not conducive to module construction and reuse. The main disadvantage is that the portability is poor. When the chip is upgraded, all the schematics need to be modified.
At present, the most widely used in practical development is the HDL language input method, which can be divided into ordinary HDL and behavioral HDL by text description design. Ordinary HDL has ABEL, CUR, etc. It supports expressions such as logic equations, truth tables, and state machines, and is mainly used for simple small designs. In medium and large projects, the behavioral HDL is mainly used, and the mainstream languages are Verilog HDL and VHDL. Both languages are standards of the Institute of Electrical and Electronics Engineers (IEEE).
Their common features are: language is not related to chip technology, it is conducive to top-down design, easy to partition and transplant modules, portability is good, It has strong logic description and simulation functions, and the input efficiency is very high. In addition to this IEEE standard language, there is also the vendor's own language. It is also possible to use HDL as the main, and the schematic diagram is supplemented by the hybrid design method to play their respective characteristics.
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