How can FPGAs be further developed in new areas such as cloud computing?

Last Update Time: 2019-12-28 10:35:31

      The basic structure of Xilinx FPGA is the same. It consists of six parts: programmable input/output unit, basic programmable logic unit, embedded block RAM, rich routing resources, underlying embedded functional unit and embedded dedicated hard. Nuclear, etc.

      However, with the development of semiconductor technology, the logic capacity of FPGA is more and more abundant, faster, and more and more hard cores are embedded, such as ARM processor, PCIe, ETHERNET, etc. In terms of process technology, Xilinx's 7 series FPGAs use 28 nm technology, UltraScale uses 20 nm, and UltraScale+ uses 16 nm. The available resources for each generation of technology are doubled compared to the previous generation.

      Xilinx's FPGA is based on SRAM's LUT look up table technology, so it needs to be reconfigured after power-on. Readings from external non-volatile memory are loaded into the internal configuration SRAM by the configuration controller. FPGA architecture: Programmable I/O (input/output unit), programmable I/O supports different IO pin configurations: IO standard, single-ended or differential, voltage slew rate and output strength, pull-up or pull-down resistors, digital Impedance (DCI), the output delay can be done using the IODELAY component.

      Configurable logic block CLB (configure logic block), configurable logic block refers to the circuit that implements various logic functions, is the basic logic unit of xilinx. In Xilinx FPGAs, each configurable logic block contains 2 slices. Each slice consists of a lookup table, registers, carry chain, and multiple selectors. Slice has two different pieces of logic: SLICEM and SLICEL. SLICEM has a versatile LUT that can be configured as a shift register, or as a ROM and RAM. Each register in the slice can be configured for use as a latch.

      The routing resources are used to connect all the cells inside the FPGA, and the length and process of the wires determine the driving capability and transmission speed of the signals on the wires. The FPGA chip has a wealth of routing resources inside, and is divided into four different categories according to the process, length, width and distribution position.

      The first type is global routing resources for the chip's internal global clock and reset/set wiring; the second is long-term resources for high-speed signals between banks; the third is short-term resources for basic logic. The logical interconnection and routing between cells; the fourth category is distributed routing resources for control signal lines such as proprietary clocks and resets.

      Clock resources are divided into global clock resources, regional clock resources, and I/O clock resources.

      (1) The global clock network is a kind of global routing resource, which can ensure that the time delay of the clock signal reaching each target logic unit is basically the same.

      (2) The regional clock network is a set of clock networks that are independent of the global clock network.

      (3) I/O clock resources can be used for local I/O serializer/deserializer circuit design. Especially useful for source synchronous interface design.

      There are two types of embedded memory for Xilinx FPGAs: dedicated block RAM (BRAM) and LUTs that can be configured as distributed RAM. BRAM (Block RAM) is a dual-port RAM, the number depends on the device. 

      Each Virtex-4 BRAM can store 18Kbit of data, support synchronous read and write operations, two ports are symmetric and completely independent, share data, each port can Change its bit width and depth as needed. BRAM can be configured as single port RAM, dual port RAM, content addressable memory (CAM), and FIFO. BRAM provides dedicated control logic for synchronous/asynchronous FIFOs where control logic such as counters, comparators, and status flags do not consume additional CLB resources.

      In FIFO mode, port A of BRAM is the read port and port B is the write port. The operation of the data stream is automatic, the user does not have to care about the addressing order of the BRAM, and WRCOUNT and RDCOUNT are derived when needed by a particular application. Users need to detect FULL and EMPTY tags. These two tag values can be set to be configured anywhere in the FIFO address segment.

      In addition to the above resources and function modules, FPGA also has clock management (MMCM): digital clock management module (DCM) and phase matching clock divider (PCMD), DSP module and so on. The DSP module provides a high performance, low power computing unit. It enables multiply-accumulate units. A dedicated transceiver module is also provided to implement serializer/deserializer (SerDes) functions such as RocketIO module, Ethernet module (Ethernet MAC) module, and ARM core.

      In short, as the internal resources of FPGAs become more and more abundant, they are widely used not only in the fields of network, telecommunications, medical, industrial, etc., but also in new fields such as data centers and cloud computing.

If you want to know more, our website has product specifications for the FPGAs, you can go to ALLICDATA ELECTRONICS LIMITED to get more information