
Allicdata Part #: | 10M08SAU169A7G-ND |
Manufacturer Part#: |
10M08SAU169A7G |
Price: | $ 900.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Intel FPGAs/Altera |
Short Description: | IC FPGA 130 I/O 169UBGA |
More Detail: | N/A |
DataSheet: | ![]() |
Quantity: | 1949 |
Lead Free Status / RoHS Status: | RoHS Compliant |
Moisture Sensitivity Level (MSL): | 3 (168 Hours) |
1 +: | $ 900.00000 |
10 +: | $ 895.00000 |
100 +: | $ 888.00000 |
1000 +: | $ 878.00000 |
10000 +: | $ 858.00000 |
Series: | MAX® 10 |
Part Status: | Active |
Lead Free Status / RoHS Status: | -- |
Number of LABs/CLBs: | 500 |
Moisture Sensitivity Level (MSL): | -- |
Number of Logic Elements/Cells: | 8000 |
Total RAM Bits: | 387072 |
Number of I/O: | 130 |
Voltage - Supply: | 2.85 V ~ 3.465 V |
Mounting Type: | Surface Mount |
Number of Gates: | -- |
Operating Temperature: | -40°C ~ 125°C (TJ) |
Package / Case: | 169-LFBGA |
Supplier Device Package: | 169-UBGA (11x11) |
Base Part Number: | 169-UBGA (11x11) |
Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us: sales@allicdata.com
1. Describe
Intel® MAX® 10 devices are single-chip, non-volatile low-cost programmable logic Device (PLD) to integrate the best set of system components.
2. Feature
1. Dual configuration flash memory for internal storage
2. User flash memory
3. Instant support
4. Integrated analog-to-digital converter (ADC)
5. Single chip Nios II soft core processor support
3. Application
1. I/O expansion,
2. Communication control plane
3. industry
4. car
5. Consumer applications.
4. Logic element and logic array block
LAB is composed of 16 logic elements (LE) and a control block in the range of LAB. LE is The smallest logic unit in the MAX 10 device architecture. Each LE has four inputs, Four-input look-up table (LUT), registers, and output logic. The four-input LUT is one The function generator of any function can be implemented with four variables.
5. Embedded multiplier and digital signal processing support
MAX 10 devices support up to 144 embedded multiplier modules. Every block Supports a single 18 × 18-bit multiplier or two separate 9 × 9-bit multipliers. Combining on-chip resources and external interfaces in MAX 10 Device, you can build a DSP system with high performance, low system cost and low power consumption energy consumption. You can use Intel MAX 10 devices alone or as a DSP device coprocessor Improve the cost performance of DSP systems. You can use the following methods to control the operation of the embedded multiplier module Options:
1. Use the Intel Quartus Prime parameter editor to parameterize related IP cores
2. Use VHDL or Verilog HDL directly to infer the multiplier System design features provided for MAX 10 devices:
3. DSP IP core:
- Finite impulse response (FIR) and other common DSP processing functions, fast Fourier transform (FFT) and numerically controlled oscillator (NCO) functions
- Commonly used video and image processing function suite
4. Complete reference design for end-market applications
5. DSP Builder for Intel FPGAs interface tool between Intel Quartus Prime Software and MathWorks Simulink and MATLAB design environment
6. DSP Development Kit
6. Embedded memory block
The embedded memory structure consists of M9K memory block columns. Each M9K The memory block of the MAX 10 device provides 9 Kb of on-chip memory, which can The operating frequency is up to 284 MHz. Embedded memory structure is composed of M9K Memory block column. Each M9K memory block of MAX 10 devices provides 9 Kb of on-chip memory. You can cascade memory blocks to form wider or deeper Logical structure. You can configure the M9K memory block as RAM, FIFO buffer or ROM. The MAX 10 device memory block is optimized for applications, such as high Throughput packet processing, embedded processor program and embedded data Store.
7. Clock and phase-locked loop
MAX 10 devices provide the following resources: global clock (GCLK) network and Phase-locked loop (PLL) with 116 MHz built-in oscillator. MAX 10 devices support up to 20 global clock (GCLK) networks and can run The frequency is up to 450 MHz. The GCLK network has high drive strength and low skew. PLL provides powerful clock management and synthesis for device clocks Management, external system clock management and I/O interface clock. this The high-precision and low-jitter PLL provides the following features:
1. Reduce the number of oscillators required on the circuit board
2. Reduce device clock pins through multiple clock frequency synthesis Single reference clock source
3. Frequency synthesis
3. On-chip clock correction
4. Jitter attenuation
5. Dynamic phase shift
6. Zero delay buffer
7. Counter reconfiguration
8. Bandwidth reconfiguration
9. Programmable output duty cycle
10. PLL cascade
11. Reference clock switching
12. ADC module drive
7. FPGA general I/O
The MAX 10 I/O buffer supports a series of programmable features. These features increase the flexibility of I/O usage and provide an alternative Reduce the use of external discrete components, such as pull-up resistors and PCI Clamping diode.
8. External memory interface
Dual-supply Intel MAX 10 devices have external memory interface solutions, Use the I/O components and UniPHY IP on the right side of the device. Using this solution, you can create an external memory interface to 16-bit SDRAM Components with error correction coding (ECC).
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