11LC080T-E/TT

11LC080T-E/TT Memory Application Field and Working Principle

The 11LC080T-E/TT memory is a static random access memory (SRAM) integrated circuit (IC) composed of 4K x 8 words, based on a 0.35 micron CMOS technological process, and is applicable for 1.65V to 1.95V. It is designed for applications that require quick read/write access, such as computers and digital processing systems.

Features

• Low power consumption in both standby and active modes
• Low noise
• High speed access
• 20ns read/write cycle
• 4K words x 8 bits of memory, one word with an 8 bit data path width
• PIN, transmission gate and flip-flop options
• High current outputs allow fanned out to a fan-in of 127
• Cascadable up to 256K x 8 bits
• Power-down modes

Characteristics

• Low power dissipation (typically 1.2mW/MHz at Vdd = 1.8V and Ta = 25°C when operating cycle of 5 MHz)
• Low charge leakage with read, write and standby
• Low power standby.

Circuit Description

A basic 11LC080T-E/TT memory block is composed of 256K x 8 words of SRAM. It is organized as 4 banks (each with 128K x 8 words) of 8 bit data path width memory. Its output transistors types include PIN (Pass-thru-SIP type) for improved noise performance, fast swing response, low power consumption and durability. It also includes a bidirectional cyclic delay register that multiplexes the output of each memory bank during read/write operations. The input and the output transmission gates of each memory block can be selected through a control address.

The 11LC080T-E/TT memory includes an internal cycle rate controller and its clock frequencies can vary according to the CPU clock frequency and other device parameters. The read/write operations are typically accomplished in 20ns with 20ns latency. All SRAM blocks have a built-in power-down feature that keeps the underlying memory in a low power consumption standby mode. All banks are controlled by a common address bus and data bus.

Working Principle

In order to access the data in any 11LC080T-E/TT memory bank, the addresses of respective memory blocks need to be provided. First, the address valid bit of each memory needs to be set to 1 in order to make it valid. After the address is valid, the data lines are multiplexed such that the data bus can be used for either reading or writing. For reading, the data lines will contain data indicating the value stored in the memory. For writing, the data on the lines will be written to the addresses specified by the address bus.

When the read operation is complete, the address valid bit will be reset to 0. This will deactivate the memory and make it ready for the next reading/writing operation. During a write operation, the data will be written to the memory location specified by the address. The write operation is usually completed with the write cycle’s duration. After the write operation is completed, the address valid bit will be reset to indicate that the memory block is ready for the next address.

The 11LC080T-E/TT memory has an on-chip power-down mode that puts the memory into a low power consumption standby mode when not in use. When the power-down mode is activated, no valid address will be accepted and all internal signals are masked. In addition, the active address valid bit is reset to 0 to prevent any further data access. The power-down mode can be enabled by setting the power-down bit to 1 and then resetting it to 0. The 11LC080T-E/TT memory block will automatically enter the low power mode after the required number of cycles.