74AVCH8T245BQ,118

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1. Describe

The 74AVCH8T245 is an 8-bit dual-supply transceiver that enables bidirectional level translate. It has two 8-bit input and output ports (An and Bn), a direction control input (DIR), output enable input (OE), and dual power supply pins (VCC(A) and VCC(B)). VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V, allowing the device to Works with any low voltage node (0.8 V, 1.2 V, 1.5 V, 1.8 V,2.5V and 3.3V). Pins An, OE and DIR are referenced to VCC(A) and pin Bn is Refer to VCC(B). HIGH on DIR allows transfers from An to Bn and LOW DIR allows transfers from Bn to An. An output enable input (OE) can be used for The output is disabled, effectively isolating the bus. The device is fully suitable for partial power down applications using IOFF. IOFF circuit disables the output, preventing any damaging backflow current from passing through When the device is powered off. When VCC(A) or VCC(B) is in Suspend Mode GND level, both the An and Bn outputs are in a high-impedance shutdown state. bus station The circuits on the power-up side are always active. The 74AVCH8T245 has an active bus hold circuit to hold unused or Floating data input at a valid logic level. This function requires no external Pull-up or pull-down resistor.

2. Features

    1. Wide supply voltage range:

        - VCC(A): 0.8V to 3.6V

        - VCC(B): 0.8V to 3.6V

    2. Compliant with JEDEC standards:

        - JESD8-12 (0.8 V to 1.3 V)

        - JESD8-11 (0.9 V to 1.65 V)

        - JESD8-7 (1.2 V to 1.95 V)

        - JESD8-5 (1.8 V to 2.7 V)

        - JESD8-B (2.7V to 3.6V)

    3. ESD protection:

        - HBM JESD22-A114E Class 3B over 8000 V

        - MM JESD22-A115-A over 200 V

        - CDM JESD22-C101C over 1000 V

    4. Maximum data rate:

        - 380 Mbit/s (≥ 1.8 V to 3.3 V conversion)

        - 260 Mbit/s (≥ 1.1 V to 3.3 V conversion)

        - 260 Mbit/s (≥ 1.1 V to 2.5 V conversion)

        - 210 Mbit/s (≥ 1.1 V to 1.8 V conversion)

        - 150 Mbit/s (≥ 1.1 V to 1.5 V conversion)

        - 100 Mbit/s (≥ 1.1 V to 1.2 V conversion)

    5. Pause mode

    6. Bus hold data input

    7. Latch-up performance over 100 mA per JESD 78 Class II

    8. Input accepts voltages up to 3.6 V

    9. IOFF circuit provides partial power-down mode operation

  10. A variety of packaging options

  11. Specify from -40 °C to +85 °C and -40 °C to +125 °C

3. Pin configuration

4. Pin Description