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Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers

The CDCM6208V1HRGZR is an integrated timing solution that combines a flexible frequency synthesizer engine, a wideband low jitter pulse-width modulator (PWM), a wideband high quality low jitter clock oscillator, and a low jitter clock buffer in a single component. It is designed for use in a wide range of applications where high precision, low jitter clock signals are required. It applications include but not limit to optical networking, storage networking, clocking/timing of FPGA, ASIC, and digital signal processors (DSPs), low-voltage differential signaling (LVDS).

CDCM6208V1HRGZR Features

• Low jitter – 10 MHz to 200 MHz clock outputs
• Internal VCO covers frequency range 2.2 GHz to 3.0 GHz
• Programmable PWM outputs with up to 200 MHz bandwidth
• Four configurable clock outputs with fractional-N PLL and 8 frequency outputs
• Integrated clock buffer on die
• Flexible clock output divide configuration up to 1/64th rate

CDCM6208V1HRGZR Application Field

The applications of the CDCM6208V1HRGZR cover a wide range of areas including: Networking equipment, networking gadgets, communications systems, point of sale systems, medical equipment, X-ray equipment, control systems, office automation systems, security systems, factory automation, automotive and military systems. These systems require low noise, low jitter and precise timing signals to operate correctly.

CDCM6208V1HRGZR Working Principle

The main purpose of the CDCM6208V1HRGZR is to provide timing signals with minimal jitter for application such as high performance FPGAs, ASICs and DSPs. The clock generator is a combination of a high quality low jitter clock oscillator, a wideband low jitter pulse-width modulator and a flexible frequency synthesizer engine, all integrated on one chip. It provides a clock output frequency up to 200 MHz. The frequency synthesis engine provides 48 clock outputs with frequencies from 1 to 200 MHz and configurable pulse-width modulation (PWM) outputs from 20 to 200 MHz.

The custom circuit design of the CDCM6208V1HRGZR incorporates advanced techniques to ensure that the frequency and duty cycle of the clock outputs are precise, low jitter and noiseless. The low jitter clock is extremely important for fair communication between components, in order to prevent decode errors due to timing issues. The CDCM6208V1HRGZR supports very small jitter of 0.25 psec (or 250 fs).

Conclusion

The CDCM6208V1HRGZR is an integrated timing solution that combines a flexible frequency synthesizer engine, a wideband low jitter pulse-width modulator (PWM), a wideband high quality low jitter clock oscillator, and a low jitter clock buffer in a single component. It is designed for a wide variety of applications such as optical networking, storage networking, and clocking/timing of FPGAs, ASICs and DSPs. The CDCM6208V1HRGZR provides clock outputs with frequencies up to 200 MHz, and low jitter of 250 fs.

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