DS1100U-20+

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The DS1100U-20+ is a highly specialized integrated circuit device marketed under Maxim Integrated’s Clock/Timing - Delay Lines product line. It provides ultra-precision delay lines that are designed to introduce delays with the closest tolerance possible under the given conditions. This device has applications where the size, low power and low temperature characteristics are of prime importance. It is used in numerous timing, sampling, and equalization circuits, as well as in communication protocols, and critical measurement and calibration operations.

The DS1100U-20+\'s delay line architecture enables a short delay of up to 1.6 ns with this device. Its internal memory stores up to 16 million bit times of data, arranged in 32K x 32 bit formats. It enables programmability of data delay and eliminates the need for external delay line components. The device also provides a fast increase in speed as well as a smooth & precise operation.

The DS1100U-20+ has a wide application field, including high speed data transmission, frequency selectivity, high-speed sampling & measurement control, ultra-short delay timing, and digital signal interception. It can measure small differences of delay times to very small fractions of a nanosecond, and is a highly suitable delay line electronics for fields such as communication, defense and aerospace.

The DS1100U-20+ uses a Very Long Instruction Word (VLIW) architecture enabling delays to be adjusted in 1 nanosecond increments. It is capable of sampling any signal up to 1 GHz. The master clock rate provided by the device is configurable and can range from 8 MHz to 200 MHz, enabling operators to tailor their needed clock rate according to their specification.

The device also features the Zero Time Calibration System which is an important application designed in hardware to optimize calibration accuracy of the delay element. This system uses a high precision, low-noise amplification circuit to scale the signal amplitude, which helps the accuracy and repeatability of calibrations. The ZTC occurs at exact known points in time, allowing precise adjustments while in operation without the need for additional hardware components.

The device also implements a Delay Locked Loop with Multi-Frequency Detector (DLLMFD). The DLLMFD provides a “verifiable” signal detection and processing capability, which allows precise digital timing and sample extraction of a signal. The DLLMFD design also allows for programmable sample extraction so the signal can be adjusted to any arbitrary level. The digital timing can further be adjusted to the exact signal source frequency.

The DS1100U-20+ also integrates a wide range of peripherals, such as a Programmable Delay Block (PDB), trigger input/output outputs, low jitter clock/data converter, programmable delays and a wide range of other customizable digital signal processing functions. The PDB allows for repeatable delay sensing within a wide range of signal frequencies and has a three-stage delay logic with a programmable logical configuration. Trigger inputs are available that are externally programmable and support up to eight different trigger signals.

The low jitter clock/data converter is the most important feature of the DS1100U-20+, which has been designed for communication systems. The converter provides a data translation service that can reduce jitter from an input signal and output a clock signal with the same frequency. This converter can also be used for ultra-short waveform discrimination of signals.

In summary, the DS1100U-20+ is an ideal delay line device for applications where ultra-precision delays must be introduced with the greatest level of accuracy and tolerance. It comprises of features such as Zero Time Calibration System, Delay Locked Loop, Multi-Frequency Detector and a wide range of peripherals, which provide the necessary tools to achieve excellent performance in many critical applications.

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