F28M35H52C1RFPQ

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1. Describe

The Concerto family is a multi-core system-on-chip microcontroller unit (MCU) with independent communication and real-time control subsystems. The F28M35x family of devices is the first in the Concerto family. The communication subsystem is based on an industry standard 32-bit Arm Cortex-M3 CPU and features a variety of communication peripherals including Ethernet 1588, USB OTG with PHY, Controller Area Network (CAN), UART, SSI, I2C and an external interface . The real-time control subsystem is based on TI's industry-leading proprietary 32-bit C28x floating-point CPUs and features the most flexible and high-precision control peripherals, including ePWM with failsafe and encoder and capture—all powered by TI's TMS320C2000™ entry-level performance MCU and advanced performance MCU. Additionally, the C28-CPU has been enhanced with the addition of a VCU instruction accelerator that enables efficient Viterbi, complex arithmetic, 16-bit FFT and CRC algorithms. Shared high-speed analog subsystem and supplemental RAM memory, as well as on-chip voltage regulation and redundant clock circuits. Safety considerations also include error-correcting code (ECC), parity, and code-secure memory, as well as documentation that facilitates system-level industrial safety certification.

2. Feature

    1. Main Subsystem - Arm® Cortex®-M3

        – up to 100 MHz

        – Embedded memory

    2. Up to 512KB of Flash (ECC)

    3. Up to 32KB of RAM (ECC or parity)

    4. Up to 64KB of shared RAM

    5. 2KB IPC message RAM

        – Five Universal Asynchronous Receiver/Transmitter (UART)

        – Four Synchronous Serial Interfaces (SSI) and one Serial Peripheral Interface (SPI)

        – Two Inter-Integrated Circuits (I2C)

        – Universal Serial Bus On-the-Go (USB-OTG) + PHY

        – 10/100 ENET 1588 MII

        – Two Controller Area Networks, D_CAN, Modules (pin bootable)

        – 32-channel Micro Direct Memory Access (µDMA)

        – Dual security zones (128-bit password per zone) 

        – External Peripheral Interface (EPI)

        – Micro Cyclic Redundancy Check (µCRC) module

        – Four general purpose timers

        – Two watchdog timer modules

        – Three external interrupts

        – Endian: little endian

    6. Clock

        – On-chip crystal oscillator and external clock input

        – Supports dynamic phase-locked loop (PLL) ratio changes

    7. 1.2-V digital, 1.8-V analog, 3.3-V I/O design

    8. Interprocessor Communication (IPC)

        – 32 handshake channels

        – Four channels generate IPC interrupts

        – Can be used to coordinate data transfer via IPC message RAM

    9. Up to 74 individually programmable multiplexed general-purpose input/output (GPIO) pins

        – Trouble-free I/O

  10. Control Subsystem - TMS320C28x 32-bit CPU

        – up to 150 MHz

        – C28x kernel hardware built-in self-test

        – Embedded memory

  11. Up to 512KB of Flash (ECC)

  12. Up to 36KB of RAM (ECC or parity)

  13. Up to 64KB of shared RAM

  14. 2KB IPC message RAM

        – IEEE-754 single-precision floating-point unit (FPU)

        – Viterbi, Complex Math, CRC Unit (VCU)

        – Serial Communication Interface (SCI)

        – SPI

        – I2C

        – 6-channel direct memory access (DMA)

        – Nine Enhanced Pulse Width Modulator (ePWM) modules

  15. 18 outputs (16 high resolution)

        – Six 32-bit enhanced capture (eCAP) modules

        – Three 32-bit Enhanced Quadrature Encoder Pulse (eQEP) modules

        – Multichannel Buffered Serial Port (McBSP)

        – EPI

        – A secure area (128-bit password)

        – Three 32-bit timers

        – Endian: little endian

  16. Simulation subsystem

        – Dual 12-bit analog-to-digital converters (ADCs)

        – Up to 2.88 MSPS

        – Up to 20 channels

        – Four sample and hold (S/H) circuits

        – Up to 6 comparators with 10 digital-to-analog converters (DACs)

  17. pack

        – 144-Pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flat Package (HTQFP)

  18. Temperature options:

        – T: –40°C to 105°C Junction

        – S: –40°C to 125°C Junction

        – Q: –40°C to 125°C free air (AEC Q100 certification for automotive applications)

3. Application

    1. Automatic sorting equipment

    2. CNC control

    3. Central inverter

    4. String inverter

    5. AC drive control module

    6. Servo drive control module

    7. AC input brushless DC motor drive

    8. DC input brushless DC motor drive

    9. Industrial AC-DC

  10. Three-phase UPS

4. Cortex-M3 Controller Area Network

    CAN is a serial communication protocol that effectively supports highly secure distributed real-time control. CAN implements the following functions:

    1. CAN Protocol Version 2.0 Parts A, B

    2. Bit rates up to 1 Mbit/s

    3. Multiple clock sources

    4. 32 message objects

    5. A separate identifier mask for each message object

    6. Programmable FIFO mode for message objects

    7. Programmable loopback mode for self-test operation

    8. Suspend mode for debugging support

    9. Software module reset

  10. Automatic bus-on by programmable 32-bit timer after bus-off state

  11. Message RAM parity mechanism

  12. Two interrupt lines

  13. Global power-down and wake-up support

5. Functional Description

The USB controller provides full OTG negotiation by supporting both the SRP and the HNP. The SRP allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used after the initial session request protocol has powered the bus and provides a method to determine which end of the c able will act as the Host controller. When the device is connected to non-OTG peripherals or devices, the controller can detect which cable end was used and provides a register to indicate if the controller should act as the Host controller or the Device controller. This indication and the mode of operation are handled automatically by the USB controller. This autodetection allows the system to use a single A/B connector instead of having both A and B connectors in the system, and supports full OTG negotiations with other OTG devices. In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers. The USB controller can be configured to act as either a dedicated Host or Device, in which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal.