Allicdata Part #: | ICS280PGI-ND |
Manufacturer Part#: |
ICS280PGI |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | IDT, Integrated Device Technology Inc |
Short Description: | IC CLK SYNTH TRPL PLL 16-TSSOP |
More Detail: | N/A |
DataSheet: | ICS280PGI Datasheet/PDF |
Quantity: | 1000 |
1 +: | 0.00000 |
Differential - Input:Output: | No/No |
Base Part Number: | ICS280 |
Supplier Device Package: | 16-TSSOP |
Package / Case: | 16-TSSOP (0.173", 4.40mm Width) |
Mounting Type: | Surface Mount |
Operating Temperature: | -40°C ~ 85°C |
Voltage - Supply: | 3.135 V ~ 3.465 V |
Divider/Multiplier: | Yes/Yes |
Frequency - Max: | 200MHz |
Series: | VersaClock® |
Ratio - Input:Output: | 1:4 |
Number of Circuits: | 1 |
Output: | CMOS |
Input: | Clock, Crystal |
PLL: | Yes with Bypass |
Type: | Clock/Frequency Synthesizer, Fanout Distribution, Spread Spectrum Clock Generator |
Part Status: | Obsolete |
Packaging: | Tube |
Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us: sales@allicdata.com
The ICS280PGI is a universal clock generator, programmable phase-locked loop (PLL), and frequency synthesizer, providing a powerful and practical solution for clock and timing requirements. It is designed for use in a wide variety of applications, which require low power, low cost, and low jitter.
To provide the widest range of flexibility and simplicity of use, the ICS280PGI have several input and output interfaces including LVCMOS PLL, LVDS, and HDMI. The device features programmable output frequency ranges of 10 MHz to 400 MHz, programmable output phase shift up to 1.25°, and programmable duty cycle between odd and even cycle of clocks.
The main feature of the ICS280PGI is its high performance, low power, and low jitter. The device features a maximum power consumption of 8.3 mW, a maximum jitter of 0.01ns, and a minimum tbo of 0.50ps. With such a low power consumption and jitter, the device can be used in a variety of applications without compromising performance.
The ICS280PGI is also designed with an integrated programmable PLL that enables the frequency of an input clock to be changed. This allows the device to be used in a variety of clock tolerant applications such as telecommunications, computing, and consumer electronics. The device is also designed with an integrated programmable frequency synthesizer that enables the device to generate frequencies from 10 MHz to 400 MHz in steps of 1/100 of a percent.
The ICS280PGI also features integrated feedback logic and an adjustable digital filter (DSP). The feedback logic is used to allow the device to be used in closed-loop clock control applications. The adjustable digital filter (DSP) is used to reduce the amount of noise generated by the device. By utilizing a combination of these features, the ICS280PGI is able to provide the highest level of flexibility and performance of any clock generator or frequency synthesizer available.
The ICS280PGI is designed with an automatic voltage regulation (AVR) system. This ensures the device will maintain its performance under varying conditions. The device also features a temperature compensated crystal oscillator (TCXO). The TCXO provides increased accuracy and stability of the device under varying temperatures. The ICS280PGI is also designed with several other features such as integrated watchdog timer and a dual clock/chip enable inputs.
In summary, the ICS280PGI is a powerful, low power and low jitter clock generator, programmable PLL, and frequency synthesizer. It is designed to be used in a variety of clock tolerant applications. The device features programmable output frequency ranges of 10 MHz to 400 MHz and programmable output phase shift up to 1.25°. The ICS280PGI also features integrated feedback logic and adjustable digital filters (DSP) for increased flexibility and performance. The device also features temperature compensated oscillator (TCXO) for accurate and stable operation. The ICS280PGI is designed with a variety of features to provide maximum flexibility and performance of clock and timing requirements.
The specific data is subject to PDF, and the above content is for reference
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