IS42S16160J-6TLI Allicdata Electronics
Allicdata Part #:

IS42S16160J-6TLI-ND

Manufacturer Part#:

IS42S16160J-6TLI

Price: $ 2.43
Product Category:

Integrated Circuits (ICs)

Manufacturer: ISSI, Integrated Silicon Solution Inc
Short Description: IC DRAM 256M PARALLEL 54TSOPSDRAM Memory IC 256Mb ...
More Detail: N/A
DataSheet: IS42S16160J-6TLI datasheetIS42S16160J-6TLI Datasheet/PDF
Quantity: 23241
1 +: $ 2.43000
10 +: $ 2.35710
100 +: $ 2.30850
1000 +: $ 2.25990
10000 +: $ 2.18700
Stock 23241Can Ship Immediately
$ 2.43
Specifications
Series: IS42S16160
Packaging: Tray 
Part Status: Active
Memory Type: Volatile
Memory Format: DRAM
Technology: SDRAM
Memory Size: 256Mb (16M x 16)
Clock Frequency: 166MHz
Write Cycle Time - Word, Page: --
Access Time: 5.4ns
Memory Interface: Parallel
Voltage - Supply: 3 V ~ 3.6 V
Operating Temperature: -40°C ~ 85°C (TA)
Mounting Type: Surface Mount
Package / Case: 54-TSOP (0.400", 10.16mm Width)
Supplier Device Package: 54-TSOP II
Base Part Number: IS42S16160
Description

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com


1. DESCRIPTION

The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x8); A0-A8 (x16) provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’s will provide valid data when the DQM signal was registered LOW. A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A9 (x8); A0-A8 (x16). Whether or not AUTO-PRECHARGE is used is determined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. A memory array is written with corresponding input data on DQ’s and DQM input logic level appearing at the same time. Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0, BA1 can be used to select which bank is precharged or they are treated as “Don’t Care”. A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which is the period required for bank precharging. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enable the AUTO PRECHARGE function in conjunction with a specific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed.

2. FEATURES

    1. Clock frequency: 166, 143, 133 MHz

    2. Fully synchronous; all signals referenced to a positive clock edge

    3. Internal bank for hiding row access/precharge

    4. Single Power supply: 3.3V + 0.3V

    5. LVTTL interface

    6. Programmable burst length

        – (1, 2, 4, 8, full page)

    7. Programmable burst sequence: Sequential/Interleave

    8. Auto Refresh (CBR)

    9. Self Refresh

  10. 8K refresh cycles every 32 ms (A2 grade) or 64 ms (commercial, industrial, A1 grade)

  11. Random column address every clock cycle

  12. Programmable CAS latency (2, 3 clocks)

  13. Burst read/write and burst read/single write operations capability

  14. Burst termination by burst stop and precharge command

3. OPTIONS

    1. Package:

        - 54-pin TSOP-II

        - 54-ball BGA

    2. Operating Temperature Range:

        - Commercial (0°C to +70°C)

        - Industrial (-40°C to +85°C)

        - Automotive Grade A1 (-40°C to +85°C)

        - Automotive Grade A2 (-40°C to +105°C)



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