MC9S08AW60CPUE

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1. Describe

The MC9S08AW60, MC9S08AW48, MC9S08AW32, and MC9S08AW16 are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in this family use the enhanced HCS08 core and are available in various modules, memory sizes, memory types and package types.

2. 8-bit HCS08 central processing unit (CPU)

    1. 40-MHz HCS08 CPU (Central Processing Unit)

    2. 20 MHz internal bus frequency

    3. HC08 instruction set added BGND Instructions

    4. Single-wire background debug mode interface

    5. Breakpoint functionality that allows individual breakpoints set during in-circuit debugging (plus two more breakpoints in the on-chip debug module)

    6. On-chip real-time in-circuit emulation (ICE) with Two comparators (plus one in BDM), nine Trigger mode and on-chip bus capture buffer. Usually shows about 50 instructions Before or after the trigger point.

    7. Supports up to 32 interrupt/reset sources

3. Input Output

    1. Up to 54 general-purpose input/output (I/O) pins

    2. Software selectable pull-up on port when used as input

    3. Software selectable port slew rate control when used as output

    4. Software selectable drive strength on port when used as output

    5. Master reset pin and power-on reset (POR)

    6. Internal pull-up resistors on RESET, IRQ, and BKGD/MS pins reduce customer system cost

4. Peripherals

    1. ADC – up to 16-channel, 10-bit analog-to-digital converter with automatic compare

    2. SCI – two serial communication interface modules with optional 13-bit interrupt

    3. SPI — Serial Peripheral Interface Module

    4. IIC – Inter-Integrated Circuit Bus Module, operates at speeds up to 100 kbps at maximum bus load; enables higher baud rates at lower loads

    5. Timers – One 2-channel and one 6-channel 16-bit timer/pulse-width modulator (TPM) modules: 

        - optional input capture, output compare, and edge-aligned PWM functions on each channel. 

        - Each timer module can be configured as buffered, centered PWM (CPWM) on all channels

    6. KBI – Up to 8-pin keyboard interrupt module

5. Enable active BDM in stop mode

Entrance to active background mode from run mode is allowed if the ENBDM bit in BDCSCR is set. If ENBDM is set when the CPU executes a STOP instruction, the system clock to the background debug logic is still active when the MCU enters stop mode, so background debug communication can still occur. Additionally, the voltage regulator does not enter its low-power standby state, but maintains full internal regulation. if the user Try to enter stop2 after ENBDM setup, MCU will enter stop3 instead. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in stop or wait mode. If the ENBDM bit is set, the Background command can be used to wake the MCU from stop and into active background mode. After entering background debugging mode, all background commands are available.