PL133-67OC

Series:	--
Packaging:	Tube
Part Status:	Active
Type:	Fanout Buffer (Distribution)
Number of Circuits:	1
Ratio - Input:Output:	1:6
Differential - Input:Output:	No/No
Input:	LVCMOS
Output:	LVCMOS
Frequency - Max:	150MHz
Voltage - Supply:	2.25 V ~ 3.63 V
Operating Temperature:	0°C ~ 70°C
Mounting Type:	Surface Mount
Package / Case:	16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package:	16-TSSOP
Base Part Number:	PL133

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Introduction

The PL133-67OC is an integrated circuit (IC) designed to buffer and drive clocks in digital and analog systems. PL133-67OC belongs to the Clock/Timing - Clock Buffers, Drivers family. This application note will provide an overview of the device, describe its architecture and explain its working pricipal.

Architecture

The PL133-67OC\'s core is an advanced low power, low jitter PLL. Thje PLL contains a CMOS-based oscillator that can support clocking frequencies up to 133 MHz. It also contains a pair of complementary differential input drivers, as well as an output driver that can support up to 3.3V or 5.0V logic levels. The adjustable output delay line can provide up to 8ns of additional delay.The PL133-67OC has two external connections: an input and an output. The input connection accepts a clock signal and the output drives a clock signal. The device is based on a 3-stage buffer architecture, consisting of a pre-driver, a voltage-controlled oscillator, and an output driver. The pre-driver functions to isolate the clock signal from the PLL, reducing jitter and providing additional noise immunity. The voltage-controlled oscillator (VCO) is used to adjust the frequency or phase of the clock, and the output driver provides the necessary current to drive the clock signal.

Working Principle

The PL133-67OC operates based on the following principle: an input clock signal is supplied to the device, which is buffered by the pre-driver stage. The buffered signal is then supplied to the VCO, which adjusts the frequency or phase of the signal based on the user-adjustable parameters. Finally, the adjusted signal is supplied to the output driver, which drives the clock signal at the desired logic levels.The adjustable parameters of the device are set through two control pins, VCTRL and RTUN. The VCTRL pin is used to control the frequency of the clock, while the RTUN pin is used to adjust the phase of the clock. Additionally, the PL133-67OC has two additional pins—RDLY and GDLY—which are used to control the output delay line.

Conclusion

In conclusion, the PL133-67OC is a high-performance integrated circuit designed for buffering and driving clocks in digital and analog systems. It features an advanced low-power, low-jitter PLL, an adjustable output delay line and adjustable input parameters, which enable the device to be tuned for precise timing requirements. The PL133-67OC is an ideal solution for applications requiring high-speed clock signal buffering and driving.

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