PL138-28SI Allicdata Electronics
Allicdata Part #:

PL138-28SI-ND

Manufacturer Part#:

PL138-28SI

Price: $ 0.00
Product Category:

Integrated Circuits (ICs)

Manufacturer: Microchip Technology
Short Description: IC CLK BUFFER 1:2 1GHZ 32LQFP
More Detail: Clock Fanout Buffer (Distribution) IC 1:2 1GHz 8-S...
DataSheet: PL138-28SI datasheetPL138-28SI Datasheet/PDF
Quantity: 1000
1 +: 0.00000
Stock 1000Can Ship Immediately
$ 0
Specifications
Series: --
Packaging: Tube 
Part Status: Discontinued at Digi-Key
Type: Fanout Buffer (Distribution)
Number of Circuits: 1
Ratio - Input:Output: 1:2
Differential - Input:Output: Yes/Yes
Input: CML, HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, SSTL
Output: LVPECL
Frequency - Max: 1GHz
Voltage - Supply: 2.375 V ~ 3.63 V
Operating Temperature: -40°C ~ 85°C
Mounting Type: Surface Mount
Package / Case: 8-SOIC (0.154", 3.90mm Width)
Supplier Device Package: 8-SOP
Base Part Number: PL138
Description

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Clock buffers, drivers and PL138-28SI extend, divide, translate and several other functions needed to properly distribute and process clock signals in system designs. A PL138-28SI is generally used to fan a single clock source out to multiple devices where each device will consume a fraction of the original frequency. This can be accomplished with a single fan-out buffer, like a PL138-28SI, or multiple fan-outs of various sizes.

The PL138-28SI clock buffer is a low skew 2:1 Clock Driver. This device is designed to provide dual clocks for a variety of applications. The input clock can be connected to the inputs PI-1, PI-2 and the two outputs PO-1, PO-2 are buffered versions of the same clock. The PL138-28SI is constructed from two identical circuits, optimized for low skew operation.

The PL138-28SI will operate from 2.3V to 3.3V supplies and can tolerate up to 5.5V on all pins. The device will drive outputs up to 3.3V and is capable of sinking 24mA. The PL138-28SI is available in the standard 1.27mm pitch TSSOP-8 package.The main application fields of PL138-28SI are Computer, Mobile & Digital Audio, Automotive, and Broadcast TV & Cable TV. It is suitable for driving highspeed synchronous devices, such as digital signal processors, memory and FPGAs with synchronous clocking. The working principles of PL138-28SI are quite simple and effective. It uses low all-pass-filtering on the input signal to reduce non-harmonic distortion and clock jitter, and compensates for signal loss in long lines by using advanced built-in buffering techniques. Additionally, the device features an automatic gain control circuitry, which eliminates the need for manual tuning of the signal level.

In summary, the PL138-28SI device is an efficient and easy-to-use clock buffer. It can drive multiple devices without any degradation of the clock signal. It is suitable for a variety of applications such as computers, mobile and digital audio, automotive, and broadcast and cable TV.

The specific data is subject to PDF, and the above content is for reference

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