SI5335A-B04087-GMR

Series:	*
Packaging:	Tape & Reel (TR)
Part Status:	Active
Mounting Type:	Surface Mount
Package / Case:	24-VFQFN Exposed Pad
Supplier Device Package:	24-QFN (4x4)

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The SI5335A-B04087-GMR is a clock generator, PLL, and frequency synthesizer capable of generating signals ranging in frequency from 10 MHz to 1040 MHz with a minimumVCOdivider of 2. It is suitable for a wide range of applications, such as clock and data recovery, Synchronous Optical Network (SONet), carrier and line synchronization, and Ethernet.The SI5335A-B04087-GMR is an integrated clock processing device designed for low jitter clock distribution. It is capable of generating a wide range of clock signals for applications requiring precision frequency and phase generation. Its integrated PLL and frequency synthesizer allow the device to be used in multiple applications such as clock and data recovery, Synchronous Optical Network (SONet), carrier and line synchronization and Ethernet.The SI5335A-B04087-GMR features an integrated low-noise programmable PLL which can be used to generate clock outputs off a single crystal reference clock input. The frequency synthesizer allows the device to generate multiple output clocks which can be synchronized with different frequencies in different applications. The device also supports phase-locked loop (PLL) reset and power down functions.The SI5335A-B04087-GMR includes a phase-locked loop (PLL) core which is composed of a voltage-controlled oscillator (VCO), divider circuits, phase frequency detectors and loop filters. The VCO is designed to have a maximum operating frequency that is four times that of the input reference frequency. The VCO frequency can be divided down to match the frequency of the reference or to generate a clock signal of higher frequency than that of the reference.The phase frequency detector (PFD) and loop filter determine the phase difference between a generated clock signal and the reference clock. The PFD compares the phase difference between a generated input clock signal and a reference clock signal, and outputs a difference signal to the loop filter. The loop filter smoothes out the phase jitter and eventually controls the phase difference between the generated clock and the reference clock.The SI5335A-B04087-GMR supports three types of output formats: LVCMOS, LVDS and HCSL. The LVDS and HCSL outputs are designed for low jitter performance and provide static output mid-voltages for improved noise integrity. The HCSL outputs also feature active ground sensing for improved jitter performance.The SI5335A-B04087-GMR is designed to provide low jitter and reliable performance in a wide variety of applications. It is capable of generating precision frequency and phase outputs over a designated frequency range, and supports power down and PLL reset functions. Its integrated PLL and frequency synthesizer allow the device to be used in multiple applications such as clock and data recovery, SONET, carrier and line synchronization and Ethernet.

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