SI5335A-B06421-GMR

Series:	*
Packaging:	Tape & Reel (TR)
Part Status:	Active
Mounting Type:	Surface Mount
Package / Case:	24-VFQFN Exposed Pad
Supplier Device Package:	24-QFN (4x4)

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Application Field and Working Principle of SI5335A-B06421-GMR

The SI5335A-B06421-GMR is an orphaned clock generator providing a variety of low-jitter clock solutions for telecom and low-jitter system clock applications. It is classified as a clock/timing device, and specifically as a clock generator, PLL, frequency synthesizer and jitter cleaner. This device is suited for multiple applications involving high-precision timing for processing and data transfer.

General Description

The SI5335A-B06421-GMR is a clock generator with dual-PLL and integrated jitter cleaner (JTS). Operating in chip and pin packages, it is best suited for repeatable, low-jitter clock solutions. It features a +1.5V LVCMOS compatible buffered output and requires only a single reference clock. Common applications are the generation of 16 kHz or 32 kHz reference clocks and 26 MHz or 27 MHz clock solutions.

Features & Benefits

The SI5335A-B06421-GMR includes some of the following features that enable it to suit a variety of applications:

• Frequency selectable output
• Package size is 6mmx6mm
• Low-jitter binary output
• Integrated jitter cleaner (JTS)
• Dual-PLL ring architecture
• High frequency output of 25 MHz
• Programmable output frequency
• Output frequencies include 16 kHz and 32 kHz
• Clock multiplier solution
• Supply voltage of +1.5V
• Ability to meet jitter mask requirements to EN/IEC/CCSA

Working Principle

The SI5335A-B06421-GMR consists of a Programmable Clock Block (PCB) and a Jitter Cleaner (JTS). The PCB is used to synthesize reference clocks with a wide operating range. The output of the PCB contains jitter. The JTS then cleans the jitter from the process output and makes it suitable for use in various applications. The Programmable Clock Block (PCB) uses two PLLs to produce two outputs of different frequencies. The two PLLs are virtually locked together via a differential signal between the two outputs. This ensures an optimal output frequency for the final signal. The PLLs used in the SI5335A-B06421-GMR are low-jitter, programmable ring-type PLLs implemented using advanced silicon-on-insulator technology. This technology allows for high frequency generation without compromising jitter performance. The JTS module is used to reduce jitter from the output signal of the PCB. It works by using a digital filter to remove unwanted jitter using a time-to-digital converter (TDC). The TDC measures the phase error between the input reference clock and the output all the way but consolidates the data results into a single jitter metric. The JTS then filters the signal using a digital filter to reduce the unwanted jitter. This ensures a low jitter output, meeting requirements to EN/IEC/CCSA standards.

Conclusion

The SI5335A-B06421-GMR is a clock/timing device classified as a clock generator, PLL, frequency synthesizer, and jitter cleaner. This device provides low-jitter clock solutions for applications involving high-precision timing for processing and data transfer. The device includes a Programmable Clock Block and a Jitter Cleaner, both utilizing advanced technology. It has a +1.5V LVCMOS compatible output and can produce reference frequencies of 16k Hz and 32k Hz and clock frequencies of 25MHz. The integrated jitter cleaner enables it to meet jitter mask requirements to EN/IEC/CCSA standards.

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