SI5335D-B06048-GMR

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The SI5335D-B06048-GMR is a frequency synthesizer for the most demanding clock applications. It combines an integrated high performance VCO, a low noise fractional-N PLL and a frequency synthesizer output stage resulting in an extraordinary low cross-jitter performance. The multi-modulus prescaler and proprietary dithering algorithm allow the SI5335D-B06048-GMR to reach high levels of output frequency resolution at all operating frequencies. The integrated VCO provides superior jitter performance and a full dynamic frequency range up to 5.5GHz.

The SI5335D-B06048-GMR’s wide input and output frequency range, along with the high output resolution – is ideal for clock synchronization and clock targeting applications. The low jitter and low phase noise, combined with the configurable loop bandwidth and VCO selection, make this device a great choice for video clock applications.

The SI5335D-B06048-GMR is designed for data acquisition and signal processing systems, such as FPGA and DSP applications, that require high performance and fine frequency resolution. The low phase noise, moderate output frequency range and fast lock-time make it suitable for applications such as clock distribution, reference, and multiplier applications.

The working principle of the SI5335D-B06048-GMR is based on a phase-locked loop (PLL) architecture. The output of the device is a high resolution, low jitter and low phase noise clock signal. The phase-locked loop core consists of a phase frequency detector (PFD), charge pump, voltage-controlled oscillator (VCO), loop filter and a programmable digital divide-by-N counter. The clock input and the VCO are connected to the input of the phase detector, which compares the phases of the two signals. If the input frequency is higher than the VCO frequency, the phase detector sends a positive pulse to the charge pump, which raises the voltage of the loop filter, causing the VCO frequency to increase.

If the input frequency is lower than the VCO frequency, a negative pulse will be sent to the charge pump and the VCO frequency will decrease. The VCO frequency change is controlled by the loop filter, which is an integrator. The loop filter also removes any fluctuations in the input and VCO frequencies, allowing the PLL to achieve a stable frequency and phase relationship. The output of the VCO is passed to a programmable digital divide-by-N counter, which divides the VCO frequency to the required output frequency.

The SI5335D-B06048-GMR is a great choice for applications that require a high performance, ultra-low jitter, low phase-noise clock synthesizer. With its wide frequency range, low jitter and low phase-noise performance, high resolution and fast lock times, it is ideal for clock distribution, reference and clock multiplier applications.

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