| Allicdata Part #: | STM1001SBWX6F-ND |
| Manufacturer Part#: |
STM1001SBWX6F |
| Price: | $ 0.15 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | STMicroelectronics |
| Short Description: | IC RESET CIRCUIT SOT-23Supervisor Open Drain or Op... |
| More Detail: | N/A |
| DataSheet: | STM1001SBWX6F Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | $ 0.15000 |
| 10 +: | $ 0.14550 |
| 100 +: | $ 0.14250 |
| 1000 +: | $ 0.13950 |
| 10000 +: | $ 0.13500 |
| Series: | STM1001 |
| Packaging: | Reel,Cut Tape,MouseReel |
| Part Status: | Active |
| Type: | Simple Reset/Power-On Reset |
| Number of Voltages Monitored: | 1 |
| Output: | Open Drain or Open Collector |
| Reset: | Active Low |
| Reset Timeout: | 20 ms Minimum |
| Voltage - Threshold: | 2.93V |
| Operating Temperature: | -40°C ~ 85°C (TA) |
| Mounting Type: | Surface Mount |
| Package / Case: | TO-236-3, SC-59, SOT-23-3 |
| Supplier Device Package: | SOT-23-3 |
| Base Part Number: | STM1001 |
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1. Describe
The STM1001 microprocessor reset circuit is a low-power monitoring device used to monitor power supplies. It performs a single function: issues a reset signal whenever the VCC supply voltage falls below a preset value and remains active until VCC rises above a preset threshold for a minimum time
2. Feature
1. Accurate monitoring of 3 V, 3.3 V and 5 V supply voltages
2. Open-drain RST output
3. 30 ms or 140 ms reset pulse width (minimum)
4. Low Supply Current - 6 µA (typ)
5. Guaranteed RST assertion down to VCC= 1.0 V
6. Operating temperature: –40 °C to 85 °C (industrial grade)
7. Lead-free, small SOT23 package
3. Pin configuration

4. Pin Description

5. Reset output
The STM1001 microprocessor reset circuit issues a reset signal to the MCU whenever VCC is below the reset threshold (VRST). RST is guaranteed to be valid down to VCC = 1 V (0° to 70 °C). During power-up, once VCC exceeds the reset threshold, the internal timer will keep RST low for the reset timeout period, trec. After this interval, RST returns high. If VCC is below the reset threshold, RST goes low. Each time RST is asserted, it is held low for at least the reset timeout period. The internal timer is cleared whenever VCC is below the reset threshold. The reset timer starts when VCC returns above the reset threshold. Active-low reset (RST) is an open-drain output.
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STM1001SBWX6F Datasheet/PDF