TCA6424ARGJR Integrated Circuits (ICs)

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1. Describe

This 24-bit I/O expander for a two-wire bidirectional bus (I2C) is designed to provide a general purpose remote I/O expansion I2C serial interface [serial clock (SCL) and serial data (SDA) for most microcontrollers )]. The main advantage of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P port side of the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, providing level reduction to save power. In contrast to de-powering microprocessors and microcontrollers, some PCB components such as LEDs are kept at 5V.

2. Feature

    1. Operating supply voltage range from 1.65 V to 5.5 V

    2. Allows bidirectional voltage level translation and GPIO expansion:

        – 1.8-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V or 5-V P port

        – 2.5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V or 5-V P port

        – 3.3-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V or 5-V P port

        – 5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V P port

    3. I2C to parallel port expander

    4. Low standby current consumption of 1 μA

    5. Schmitt trigger action allows slow input transitions and better switching noise immunity at SCL and SDA inputs

        – Vhys = 0.18 V typical, 1.8 V

        – Typical values. 0.25 V at Vhys = 2.5 V

        – Typical values. 0.33 V at Vhys = 3.3 V

        – Vhys = 0.5 V typical, 5 V

    6. 5V tolerant I/O ports

    7. Active low reset input (RESET)

    8. Open-drain active-low interrupt output (INT)

    9. 400kHz fast I2C bus

  10. Input/Output Configuration Registers

  11. Polarity Inversion Register

  12. Internal power-on reset

  13. Configure all channels as inputs at power-up

  14. Trouble-free startup

  15. Noise filter on SCL/SDA input

  16. Latch output with high current drive capability to directly drive LEDs

  17. Latch-up performance over 100 mA per JESD 78, Class II

  18. ESD protection exceeds JESD 22

        – 2000-V mannequin (A114-A)

        – 200-V machine model (A115-A)

        – 1000V charging device model (C101)

3. Pin configuration

4. Pin Description

5. Function description

When the I/O is configured as an input, FETs Q1 and Q2 are turned off, resulting in a high impedance input. The input voltage can rise above VCC up to 5.5 V. If the I/O is configured as an output, either Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there is a low impedance path between the I/O pin and VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended level for proper operation. The bidirectional I2C bus consists of serial clock (SCL) and serial data (SDA) lines. When connected to the output stage of the device, both lines must be connected to the positive supply through pull-up resistors. Data transfers can only be initiated when the bus is not busy. I2C communication with the device is initiated by the host sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high. After the Start condition, the device address byte is sent with the most significant bit (MSB) first, including the data direction bit (R/W). After receiving a valid address byte, the device responds with an acknowledgement (ACK), SDA is low for input/output during the high period of the ACK-related clock pulse. The address (ADDR) input of the slave device must not change between start and stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock cycle, as changes on the data line are interpreted as control commands (start or stop) at this time. A stop condition, a low-to-high transition of the SDA input/output while the SCL input is high, is sent by the master. Between start and stop conditions, any number of data bytes can be transferred from the transmitter to the receiver. Each 8-bit byte is followed by an ACK bit. The transmitter must release the SDA line before the receiver can send the ACK bit. Acknowledging devices must pull the SDA line low during the ACK clock pulse so that the SDA line settles low during the high pulse of the ACK-related clock cycle. When a slave receiver is addressed, it must generate an ACK after each byte it receives. Similarly, the host must generate an ACK after each byte it receives from the sender. Setup and hold times must be met to ensure proper operation. The master receiver signals the end of data to the slave transmitter by not generating an acknowledgment (NACK) after the last byte is output from the slave device. This is done by the master receiver by holding the SDA line high. In this case, the transmitter must release the data line to allow the master to generate a stop condition.