TM4C123BE6PZIR

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1. Describe

Texas Instruments' Tiva™ C Series microcontrollers provide designers with a high-performance ARM® Cortex™-M-based architecture, extensive integration capabilities, and a robust ecosystem of software and development tools. The Tiva™ C-Series offers 80 MHz Cortex-M and FPU, various integrated memories and multiple programmable GPIOs with the performance and flexibility as a target architecture. Tiva™ C Series devices provide consumers with a cost-effective solution that minimizes board cost and design cycle time by integrating application-specific peripherals and providing a comprehensive software library. Tiva™ C-Series microcontrollers offer faster time-to-market and cost savings and are the first choice for high-performance 32-bit applications.

2. ARM Cortex-M4F processor core

All members of the Tiva™ C family, including the TM4C123BE6PZ microcontroller, are designed around the ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a high-performance, low-cost platform that addresses the need for minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computing performance and excellent system responsiveness to interrupts.

3. Analog comparator

An analog comparator is a peripheral that compares two analog voltages and provides a logic output to indicate the result of the comparison. The TM4C123BE6PZ microcontroller provides three independent integrated analog comparators that can be configured to drive outputs or generate interrupts or ADC events. The comparator can provide its output to a device pin as a replacement for the on-board analog comparator, or it can be used to signal the ADC to the application via an interrupt or trigger to start capturing a sampling sequence. Interrupt generation and ADC trigger logic are separate. This means, for example, that an interrupt can be generated on a rising edge and an ADC can be triggered on a falling edge.

4. Function Description

The JTAG module consists of a Test Access Port (TAP) controller and a serial shift chain Update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the rising edge of TCK, the sequence of values captured on TMS. The TAP controller determines when the serial shift chain captures new data, transfers the data from TDI to TDO, and updates the parallel load registers. The current state The TAP controller also determines whether the instruction register (IR) chain or one of the data register (DR) chains is being accessed. A serial shift chain with parallel load registers consists of a single instruction register (IR) chain and multiple data register (DR) chains. The current instruction register loaded in a parallel load determines which DR chain tap controller is captured, shifted, or updated during sequencing. Some instructions, such as EXTEST, operate on data currently in the DR chain and do not capture, transfer, or update any chain. Unimplemented instructions decode to BYPASS instructions to ensure that the serial path between TDI and TDO is always connected.