TM4C123GE6PZIR

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1. Describe

Texas Instruments' Tiva™ C Series microcontrollers offer designers a high-performance ARM® Cortex™-M-based architecture with broad integration capabilities and a robust ecosystem software and development tools. Targeting performance and flexibility, the Tiva™ C-Series architecture offers an 80 MHz Cortex-M with FPU, various integrated memories, and multiple programmable GPIOs. Tiva™ C Series devices provide consumers with a cost-effective solution by integrating application-specific peripherals and providing a comprehensive library of software tools to minimize board cost and design cycle time. Tiva™ C-Series microcontrollers provide faster time to-market and cost savings, and are the first choice for high-performance 32-bit applications.

2. Feature

The TM4C123GE6PZ microcontroller features a battery-backed hibernation module that effectively powers down the TM4C123GE6PZ to a low-power state during extended periods of inactivity. The sleep module features a power-up/power-down sequencer, real-time counter (RTC), multiple wake-up-from-sleep options, and dedicated battery-backed memory, making the TM4C123GE6PZ microcontroller ideal for battery-powered applications. Additionally, the TM4C123GE6PZ microcontroller benefits from ARM's widely available development tools, system-on-chip (SoC) infrastructure IP applications and large user community. In addition, microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements, thereby reducing cost. Finally, most of the TM4C123GE6PZ microcontroller code is compatible with the Tiva™ C Series product line, providing flexibility across designs.

3. Processor core

    1. 32-bit ARM Cortex-M4F architecture optimized for small embedded applications

    2. 80-MHz operation; 100 DMIPS performance

    3. Excellent processing performance combined with fast interrupt handling

    4. Thumb-2 mixed 16-bit/32-bit instruction set provides the high performance expected from a 32-bit ARM core, 

        – with the compact memory sizes typically associated with 8-bit and 16-bit devices, typically in the kilobyte range of microcontrollers memory

        – Single cycle multiply instruction and hardware divide

        – Atomic bit manipulation (bit banding) to maximize memory utilization and simplify peripheral control

        – Unaligned data access, allowing efficient packing of data into memory

    5. IEEE754 compliant single-precision floating point unit (FPU)

    6. 16-bit SIMD vector processing unit

    7. Fast code execution allows slower processor clocks or increased sleep mode time

    8. Harvard architecture is characterized by separate instruction and data busses

    9. Efficient processor cores, system and memory

  10. Hardware divide and multiply accumulate for fast digital signal processing

  11. Saturation algorithm for signal processing

  12. Deterministic, high-performance interrupt handling for time-critical applications

  13. Memory Protection Unit (MPU) provides privileged mode for protected operating system functions

  14. Enhanced system debugging with extensive breakpoint and trace capabilities

  15. Serial wire debug and serial wire trace reduce the number of pins required for debug and trace

  16. Migrating from the ARM7™ processor family for better performance and power efficiency

  17. Optimized for single-cycle flash usage at specific frequencies.

  18. Ultra-low power consumption with integrated sleep mode

4. TM4C123GE6PZ Microcontroller, ADC Module Features

    1. 22 shared analog input channels

    2. 12-bit precision ADC

    3. Single-ended and differential input configurations

    4. On-chip internal temperature sensor

    5. Maximum sample rate of 1 million samples per second

    6. Selectable phase shift for sampling time programmable from 22.5º to 337.5º

    7. Four programmable sample conversion sequencers, 1 to 8 entries in length, with corresponding conversion result FIFOs

    8. Flexible trigger control

        – Controller (software)

        – Timer

        – Analog Comparator

        –  Pulse width modulation

        – General purpose input and output interface

    9. Hardware averaging of up to 64 samples

  10. Eight digital comparators

  11. Converter uses two external reference signals (VREFA+ and VREFA-) or VDDA and GNDA as voltage references

  12. Separate power and ground for analog circuits from digital power and ground

  13. Efficient transfers using tiny direct memory access controller (µDMA)

        – Dedicated channel for each sample sequencer

        – ADC module uses burst request for DMA

5. Analog comparator

An analog comparator is a peripheral that compares two analog voltages and provides a logic output to indicate the result of the comparison. The TM4C123GE6PZ microcontroller provides three independent integrated analog comparators that can be configured to drive outputs or generate interrupts or ADC events. The comparator can provide its output to a device pin in place of the onboard analog comparator, or it can be used to send an ADC signal to the application via an interrupt or trigger to initiate a capture Sufficient sequence. Interrupt Generation and ADC Triggering The logic is separate. This means that, for example, an interrupt can be generated on a rising edge, and ADC triggers on falling edge.

6. Function Description

The JTAG module consists of the Test Access Port (TAP) controller and serial shift chain update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the rising edge of TCK, the sequence of values captured on TMS. The TAP controller determines when the serial shift chain captures new data, transfers the data from TDI to TDO, and updates the parallel load registers. The current state The TAP controller also determines whether the instruction register (IR) chain or one of the data registers (DR) chain is being accessed. A serial shift chain with parallel load registers consists of a single instruction register (IR) chain and multiple data register (DR) chains. The current instruction register loaded in a parallel load determines which DR chain tap controller is captured, shifted, or updated during sequencing. Some instructions, such as EXTEST, operate on data currently in the DR chain and do not capture, transfer, or update any chain. Unimplemented instructions decode to BYPASS instructions to ensure that the serial path between TDI and TDO is always connected.