TM4C123GE6PZT7R

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1. Describe

Tiva™ C-Series ARM Cortex-M4 microcontrollers offer top performance and advanced integration. For applications requiring extreme power savings, the TM4C123GE6PZ microcontroller Features a battery-backed hibernate module that effectively powers down the TM4C123GE6PZ to a low-power state during extended periods of inactivity. The sleep module features a power-up/power-down sequencer, a real-time counter (RTC), multiple wake-up-from-sleep options, and dedicated battery-backed memory, making the TM4C123GE6PZ microcontroller ideal for battery-powered applications. In addition, the TM4C123GE6PZ microcontroller benefits from ARM's widely available development tools, system-on-chip (SoC) infrastructure IP applications and large user community. In addition, microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements, thereby reducing cost. Finally, most of the TM4C123GE6PZ microcontroller code is compatible with the Tiva™ C Series product line, providing flexibility across designs.

2. Feature

The Synchronous Serial Interface (SSI) is a four-wire bidirectional communication interface that converts data between parallel and serial. The SSI module performs serial-to-parallel conversion on the data Receives from peripherals and performs parallel-to-serial conversion of data transmitted to peripherals. The SSI module can be configured as a master or a slave. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered using separate internal FIFOs. The SSI block also includes a programmable bit rate clock divider and prescaler to generate an output serial clock derived from the SSI block input clock. The bit rate is generated based on the input clock, and the maximum bit rate is determined by the connected peripherals. The inter-integrated circuit (I2C) bus provides bidirectional data transfer over a two-wire design (serial data line SDA and serial clock line SCL). The I2C bus connects to external I2C devices such as serial memory (RAM and ROM), network devices, LCDs, tone generators, etc. The I2C bus can also be used for system testing and diagnostic purposes in product development and manufacturing. Every device on the I2C bus can be designated as a master or a slave. The I2C module supports sending and receiving data as a master or slave, and can operate as both a master and a slave at the same time. Both I2C masters and slaves can generate interrupts. The TM4C123GE6PZ microcontroller provides 128 KB of single-cycle on-chip flash. Flash memory is organized into a set of 1 KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2 KB blocks that can be protected individually. These blocks can be marked read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, thus protecting the contents of these blocks from modification. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, thus protecting the contents of these blocks from being read by the controller or debugger.

3. Application

    1. Low-power, handheld smart devices

    2. Gaming equipment

    3. Home and commercial site monitoring

    4. Motion Control

    5. Medical equipment

    6. Test and measurement equipment

    7. Factory Automation

    8. Fire Safety

    9. Smart Energy/Smart Grid Solutions

  10. Intelligent lighting control

  11. Transportation

4. The TM4C123GE6PZ microcontroller includes four SSI modules with the following features

    1. Programmable interface operation of Freescale SPI, MICROWIRE or Texas Instruments synchronous serial interfaces

    2. Master-slave operation

    3. Programmable clock bit rate and prescaler

    4. Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep

    5. Programmable data frame size from 4 to 16 bits

    6. Internal loopback test mode for diagnostic/debug testing

    7. Standard FIFO-based interrupt and end-of-transfer interrupt

    8. Efficient transfers using tiny direct memory access controller (µDMA)

        – Separate transmit and receive channels

        – Receive single request asserted when data is in FIFO; trigger burst request when FIFO contains 4 entries

        – Send a single request when there is room in the FIFO; trigger a burst request when four or more entries can be written to the FIFO

5. The TM4C123GE6PZ microcontroller includes two CAN units with the following features

    1. CAN protocol version 2.0 part A/B

    2. Bit rates up to 1 Mbps

    3. 32 message objects with individual identifier masks

    4. Maskable interrupt

    5. Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications

    6. Programmable loopback mode for self-test operation

    7. Programmable FIFO mode enables storage of multiple message objects

    8. Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals