TM4C123GH6PZT7

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1. Describe

Texas Instruments' (TI) Tiva™ C-Series microcontrollers provide designers with a high-performance ARM® Cortex™-M-based architecture with broad integration capabilities and a robust ecosystem of software and development tools. Targeting performance and flexibility, the Tiva™ C-Series architecture offers an 80 MHz Cortex-M with an FPU, various integrated memories, and multiple programmable GPIOs. Tiva™ C Series devices provide consumers with a cost-effective solution by integrating application-specific peripherals and providing a comprehensive library of software tools to minimize board cost and design cycle time. Tiva™ C-Series microcontrollers offer faster time-to-market and cost savings and are the first choice for high-performance 32-bit applications.

2. Feature

The TM4C123GH6PZT7 microcontroller features a battery-backed hibernate module that effectively powers down the TM4C123GH6PZ to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, real-time counter (RTC), multiple wake-up from sleep options, and dedicated battery-backed memory, the sleep module makes the TM4C123GH6PZ microcontroller ideal for battery applications. In addition, the TM4C123GH6PZ microcontroller benefits from ARM's widely available development tools, system-on-chip (SoC) infrastructure IP applications, and a large user community. In addition, microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements, thereby reducing cost. Finally, most of the TM4C123GH6PZ microcontroller code is compatible with the Tiva™ C Series product line, providing flexibility across designs.

3. processor core

    1. 32-bit ARM Cortex-M4F architecture optimized for small form factor embedded applications

    2. 80-MHz operation; 100 DMIPS performance

    3. Excellent processing performance combined with fast interrupt handling

    4. Thumb-2 mixed 16-bit/32-bit instruction set provides the high performance expected from 32-bit Compact memory-sized ARM cores typically associated with 8-bit and 16-bit devices

        – Usually in Multi-kilobyte memory range for microcontroller-level applications

        – Single cycle multiply instruction and hardware divide

        – Atomic bit manipulation (bit banding) for maximum memory utilization and streamlined peripheral control

        – Unaligned data access, allowing data to be efficiently packed into memory

    4. IEEE754-compliant single-precision floating-point unit (FPU)

    5. 16-bit SIMD vector processing unit

    6. Fast code execution allows slower processor clocks or increased sleep mode time

    7. Harvard architecture is characterized by separate instruction and data busses

    8. Efficient processor cores, system and memory

    9. Hardware divide and multiply-accumulate for fast digital signal processing

  10. Saturation algorithm for signal processing

  11. Deterministic, high-performance interrupt handling for time-critical applications

  12. Memory Protection Unit (MPU) provides privileged mode functionality for protected operating systems

  13. Enhanced system debugging with extensive breakpoint and trace capabilities

  14. Serial wire debug and serial wire trace reduce the number of pins required for debug, trace

  15. Migrating from the ARM7™ processor family for better performance and power efficiency

  16. Optimized for single-cycle flash usage at specific frequencies.

  17. Ultra-low power consumption with integrated sleep mode

4. Nested Vectored Interrupt Controller (NVIC)

The TM4C123GH6PZ controller includes the ARM Nested Vectored Interrupt Controller (NVIC). NVIC and Cortex-M4F prioritize all exceptions in handler mode. Processor state is automatically stored on the stack on exceptions and automatically restored from the stack when an Interrupt Service Routine (ISR) ends. Interrupt vectors are fetched in parallel with state saving, enabling efficient interrupt entry. The processor supports tail chaining, which means that back-to-back interrupts can be performed without the overhead of state save and restore. Software can set 8 priority levels for 7 exceptions (system handlers) and 85 interrupts.

5. programmable timer

Programmable timers can be used to count or time external events that drive the timer input pins. Each 16/32-bit GPTM module provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or as a 32-bit timer or a 32-bit real-time clock (RTC). Each 32/64-bit wide GPTM module provides two 32-bit timers/counters that can be configured to operate independently as timers or event counters, or as a 64-bit timer or a 64-bit real-time clock (RTC) . Timers can also be used to trigger analog-to-digital (ADC) conversions and DMA transfers.