TPS3895ADRYR

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1. Description

The TPS3895ADRYR, TPS3896, TPS3897, and TPS3898 devices (TPS389x) are a family of very small supervisory circuits that monitor voltages greater than 500 mV with a 0.25% (typical) threshold accuracy and offer adjustable delay time using external capacitors. The TPS389x family also has a logic enable pin (ENABLE or ENABLE) to power on and off the output. With the TPS3895, for example, when the input voltage pin (SENSE) rises above the threshold and the ENABLE pin is high, then the output pin (SENSE_OUT) goes high after the capacitor- adjustable delay time. When SENSE falls below the threshold or ENABLE is low, then SENSE_OUT goes low. For truth tables, see Table 1 and Table 2. For TPS389xA versions, both SENSE and ENABLE have a capacitor-adjustable delay. The output asserts after this capacitor-adjustable delay when both SENSE and ENABLE inputs are good. The TPS389xP devices have a small, 0.2-µs propagation delay from when the enable pin asserts to when the output pin asserts, provided SENSE is above the threshold. All devices operate from 1.7 V to 6.5 V and have a typical quiescent current of 6 µA with an open-drain output rated at 18 V. The TPS389x is available in an ultra-small USON package and is fully specified over the temperature range of TJ = –40°C to 125°C.

2. Feature

    1. Very small USON (1.45 mm × 1.00 mm) package

    2. Adjustable threshold as low as 500 mV

    3. Threshold accuracy: 1% of temperature

    4. Capacitor adjustable delay time

    5. Low quiescent current: 6 µA (typical value)

    6. External enable input

    7. Open drain (rated voltage of 18 V) and push-pull output options

    8. Temperature range: –40°C to 125°C

    9. Pin compatible with MAX6895/6/7/8

3. Application

    1. DSP, microcontroller and microprocessor

    2. Laptops and desktop computers

    3. PDA and handheld products

    4. Portable and battery-powered products

    5. FPGA and ASIC

4. Pin configuration

5. Pin function

6. Feature Description

The TPS3897 and TPS3898 provide open-drain outputs. Pullup resistors must be used to hold these lines high when SENSE_OUT is asserted or SENSE_OUT is not asserted. By connecting the pullup resistors to the proper voltage rails, SENSE_OUT or SENSE_OUT can be connected to other devices at the correct interface voltage levels. The outputs can be pulled up to 18 V independent of the supply voltage (VCC). To ensure proper voltage levels, some thought should be given to choosing the correct pullup resistor values. The ability to sink current is determined by the supply voltage; therefore, if VCC = 5 V and the desired output pullup is 18 V, then to obtain a sink current of 1 mA or less (as mentioned in the Electrical Characteristics), the pullup resistor value sh It should be greater than 18 kΩ. By using wire-OR logic, any combination of SENSE_OUT can be combined into one logic signal. TPS3895 and TPS3896 provide push-pull output. The output logic is input by VCC high voltage. With this configuration, neither SENSE_OUT or ENSE_OUT output must be 0 for a specific connection target. However, all interface logic levels must be checked. of. It is a truth table that describes how to assert or cancel the assertion output. When the conditions are met, After the pre-configured delay time, the device changes the state from stop-asserted to valid. However, from assertion to assertion is executed almost immediately, with a delay of 16 µs (typical value).

7. Package overview