TPS7A1601DGNR

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com

1. Description

The TPS7A1601DGNR family of ultralow power, low-dropout (LDO) voltage regulators offers the benefits of ultra- low quiescent current, high input voltage and miniaturized, high thermal-performance packaging. The TPS7A16 family is designed for continuous or sporadic (power backup) battery-powered applications where ultralow quiescent current is critical to extending system battery life. The TPS7A16 family offers an enable pin (EN) compatible with  standard CMOS logic and an integrated open drain active-high power good output (PG) with a user-programmable delay. These pins are intended for use in microcontroller-based, battery-powered applications where power-rail sequencing is required. In addition, the TPS7A16 is ideal for generating a low-voltage supply from multicell solutions ranging from high cell-count power-tool packs to automotive applications; not only can this device supply a well- regulated voltage rail, but it can also withstand and maintain regulation during voltage transients. These features translate to simpler and more cost-effective, electrical surge-protection circuitry.

2. Features

    1. Wide Input Voltage Range: 3 V to 60 V

    2. Ultralow Quiescent Current: 5 µA

    3. Quiescent Current at Shutdown: 1 µA

    4. Output Current: 100 mA 

    5. Low Dropout Voltage: 60 mV at 20 mA

    6. Accuracy: 2%

    7. Available in:

        – Fixed Output Voltage: 3.3 V, 5 V

        – Adjustable Version from 1.2 V to 18.5 V

    8. Power-Good With Programmable Delay

    9. Current Limit and Thermal Shutdown Protections

  10. Stable with Ceramic Output Capacitors: ≥ 2.2 µF

  11. Packages: High Thermal Performance MSOP-8 and SON-8 PowerPAD™

  12. Operating Temperature Range: –40°C to 125°C

3. Applications

    1. Power Supplies for Notebook PCs, Digital TVs, and Private LAN Systems

    2. High Cell-Count Battery Packs for Power Tools and other Battery-Powered Microprocessor and Microcontroller Systems

    3. Car Audio, Navigation, Infotainment, and Other Automotive Systems

    4. Smoke and CO2 Detectors and Battery-Powered Alarm and Security Systems

4. Pin Configuration 

5. Pin Functions

6. Feature Description

1. Enable (EN)

The enable terminal is a high-voltage-tolerant terminal. A high input on EN actives the device and turns on the regulator. For self-bias applications, connect this input to the VIN terminal.

2. Regulated Output (VOUT)

The VOUT terminal is the regulated output based on the required voltage. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control the initial current through the pass element. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage recovers above the minimum start-up level.

3. Power-Good

The power-good (PG) pin is an open-drain output and can be connected to any 5-V or lower rail through an external pull-up resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than the PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If output voltage monitoring is not needed, the PG pin can be left floating or connected to GND. The power-good feature functionality is only guaranteed when VIN ≥ 3 V (VIN_(MIN))

4. PG Delay Timer (DELAY)

The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT). When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF. The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF) / IDELAY. For example, when CDELAY = 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V) / 1 µA = 11.93 ms.

5. Internal Current Limit

The fixed internal current limit of the TPS7A16 family helps protect the regulator during fault conditions. The maximum amount of current the device can source is the current limit (225 mA, typical), and is largely independent of output voltage. For reliable operation, do not operate the device in current limit for extended periods of time.

6. Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.

7. Application Information

The TPS7A16 family of ultralow power voltage regulators offers the benefit of ultralow  quiescent current, high input voltage, and miniaturized, high thermal-performance packaging. The TPS7A16 family is designed for continuous or sporadic (power backup) battery-operated applications where ultralow quiescent current is critical to extending system battery life.

8. Package overview