W25Q128JVSIQ

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1. Describe

The W25Q128JVSIQ (128M-bit) serial flash memory provides a storage solution for limited system space, pins and power. The 25Q family offers flexibility and performance devices far beyond ordinary serial flash. They are ideal for mapping code to RAM, executing code directly from Dual/Quad SPI (XIP), and storing voice, text, and data. The device operates from a single 2.7V to 3.6V supply and consumes as little as 1µA. All devices are available in space-saving packages. The W25Q128JV array is organized into 65,536 programmable pages of 256 bytes each. Up to 256 bytes can be programmed at one time. Can be erased in groups of 16 (4KB sector erase), in groups of 128 (32KB block erase), in groups of 256 (64KB block erase), or the entire chip (chip erase) remove page. The W25Q128JV has 4,096 erasable sectors and 256 erasable blocks, respectively. Small 4KB sectors allow more flexibility in applications requiring data and parameter storage. W25Q128JV supports standard serial peripheral interface (SPI), dual/quad I/O SPI: serial clock, chip select, serial data I/O0 (DI), I/O1 (DO), I/O2 and I/ O O3. W25Q128JV support for SPI clock frequencies up to 133MHz allows dual I/Os with an equivalent clock rate of 266MHz (133MHz x 2) and quad I/Os at 532MHz (133MHz x 2) when using fast read dual/quad I/Os /O x 4). These transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash. In addition, the device supports JEDEC standard manufacturer and device ID and SFDP, as well as a 64-bit unique serial number and three 256-byte security registers.

2. Feature

    1. New SpiFlash memory family

        – W25Q128JV: 128M bits/16M bytes

        – Standard SPI: CLK, /CS, DI, DO

        – Dual SPI: CLK, /CS, IO0, IO1

        – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

        – Software and hardware reset(1)

    2. Highest performance serial flash

        – 133MHz single, dual/quad SPI clock

        – 266/532MHz equivalent dual/quad SPI

        – 66MB/S continuous data transfer rate

        – minute. 100K program-erase cycles per sector

        – Over 20 years of data retention

    3. Efficient "continuous reading"

        – Continuous read with 8/16/32/64 byte newline

        – Only 8 clocks to address memory

        – Allows true XIP (execute-in-place) operations

    4. Low power consumption, wide temperature range

        – Single 2.7 to 3.6V supply

        – <1µA power down (typ)

        – -40°C to +85°C operating range

        – -40°C to +105°C operating range

    5. Flexible architecture with 4KB sectors

        – Unified Sector/Block Erase (4K/32K/64K bytes)

        – Program 1 to 256 bytes per programmable page

        - Erase/Program Suspend and Resume

    6. Advanced security features

        – Software and hardware write protection

        – Power lock

        – Special OTP protection

        – top/bottom, supplemental array protection

        – Single block/sector array protection

        – 64-bit unique ID for each device

        – discoverable parameter (SFDP) register

        – 3X256 bytes security register with OTP lock

        – Volatile and nonvolatile status register bits

    7. Space-saving packaging

        – 8-pin SOIC 208 mil

        – 16-pin SOIC 300-mil (additional /RESET pin)

        – 8-pad WSON 6x5-mm / 8x6-mm

        – 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)

        – 24 ball WLCSP

        – Contact Winbond for KGD and other options

3. Pin configuration

4. Pin Description

5. Pin Description

    1. Chip Select (/CS)

        The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high, the device is deselected and the serial data output (DO or IO0, IO1, IO2, IO3) pins are in a high impedance state. When deselected, device power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is pulled low, the device will be selected, power consumption will increase to the active level, and commands can be written to and data read from the device. After power-up, /CS must transition from high to low before new commands can be accepted. The /CS input must track the VCC supply level on power-up and power-down. This can be done using a pull-up resistor on the /CS pin if desired.

    2. Serial data input, output and IO

        The W25Q128JV supports standard SPI, dual SPI and quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write commands, addresses, or data to the device on the rising edge of the serial clock (CLK) input pin. Standard SPI also uses a unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use bidirectional IO pins to serially write commands, addresses, or data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. The Quad SPI instruction requires the non-volatile Quad Enable bit (QE) in Status Register 2 to be set. When QE=1, the /WP pin becomes IO2, and the /HOLD pin becomes IO3.

6. FUNCTIONAL DESCRIPTIONS

    1. Standard SPI Instructions

        The W25Q128JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS. 

    2. Dual SPI Instructions

        The W25Q128JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

    3. Quad SPI Instructions

        The W25Q128JV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, and “Fast Read Quad I/O (EBh). These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. When using Quad SPI instructions, the DI and DO pins become bidirectional IO0 and IO1, with the additional I/O pins: IO2, IO3.

    4. Software Reset & Hardware /RESET pin

        The W25Q128JV can be reset to the initial power-on state by a software Reset sequence. This sequence must include two consecutive instructions: Enable Reset (66h) & Reset (99h). If the instruction sequence is successfully accepted, the device will take approximately 30µS (tRST) to reset. No instruction will be accepted during the reset period. For the SOIC-16 and TFBGA packages, W25Q128JV provides a dedicated hardware /RESET pin. Drive the /RESET pin low for a minimum period of ~1µS (tRESET*) will interrupt any on-going external/internal operations and reset the device to its initial power-on state. Hardware /RESET pin has higher priority than other SPI input signals (/CS, CLK, IOs).