W25Q64FVSSIG

1. FEATURES

    1. New Family of SpiFlash Memories

        – W25Q32FW: 32M-bit / 4M-byte

        – Standard SPI: CLK, /CS, DI, DO, /WP,/Hold

        – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold

        – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

        – QPI: CLK, /CS, IO0, IO1, IO2, IO3

        – Software & Hardware Reset

    2. Highest Performance Serial Flash

        – 104MHz Single, Dual/Quad SPI clocks

        – 208/416MHz equivalent Dual/Quad SPI 

        – 50MB/S continuous data transfer rate

        – Min 100K Program-Erase cycles per sector

        – More than 20-year data retention

    3. Efficient “Continuous Read” and QPI Mode

        – Continuous Read with 8/16/32/64-Byte Wrap

        – As few as 8 clocks to address memory

        – Quad Peripheral Interface (QPI) reduces instruction overhead

        – Allows true XIP (execute in place) operation

        – Outperforms X16 Parallel Flash

    4. Flexible Architecture with 4KB sectors

        – Uniform Sector/Block Erase (4K/32K/64K-Byte)

        – Program 1 to 256 byte per programmable page

        – Erase/Program Suspend & Resume

    5. Advanced Security Features

        – Software and Hardware Write-Protect

        – Power Supply Lock-Down and OTP protection

        – Top/Bottom, Complement array protection

        – Individual Block/Sector array protection

        – 64-Bit Unique ID for each device

        – Discoverable Parameters (SFDP) Register

        – 3X256-Bytes Security Registers with OTP locks

        – Volatile & Non-volatile Status Register Bits

    6. Space Efficient Packaging

        – 8-pin SOIC/VSOP 208-mil, XSON 4x4-mm

        – 8-pad WSON 6x5-mm / 8x6-mm

        – 16-pin SOIC 300-mil (additional /RESET)

        – 24-ball TFBGA 8x6-mm(additional /RESET)

        – 12-ball WLCSP

        – Contact Winbond for KGD and other options

2. PIN CONFIGURATIONS

3. Pin Description

4. Function Description

CAV25128 device supports serial peripherals Interface (SPI) bus protocol, modes (0,0) and (1,1). This The device contains an 8-bit instruction register. instruction Table 7 lists the settings and related operation codes. Reading the data stored in CAV25128 is through Just provide the READ command and address. Write CAV25128, and WRITE Command, address and data, also need to be enabled A device that writes by first setting certain bits in the state Register, I will explain later. After the CS input pin changes from high to low, CAV25128 will accept any of the six commands The opcode will ignore all other possible 8-bit combinations. CAV25128 has an additional identification page that can be used for reading and writing Operation when the IPL bit in the status register is set To "1". Users can also choose to identify The page is permanently write-protected.