XC2S200-5PQ208C Allicdata Electronics
Allicdata Part #:

122-1234-ND

Manufacturer Part#:

XC2S200-5PQ208C

Price: $ 29.50
Product Category:

Integrated Circuits (ICs)

Manufacturer: Xilinx Inc.
Short Description: IC FPGA 140 I/O 208QFP
More Detail: N/A
DataSheet: XC2S200-5PQ208C datasheetXC2S200-5PQ208C Datasheet/PDF
Quantity: 6610
Lead Free Status / RoHS Status: RoHS non-compliant
Moisture Sensitivity Level (MSL): 3 (168 Hours)
1 +: $ 29.50000
10 +: $ 28.61500
100 +: $ 28.02500
1000 +: $ 27.43500
10000 +: $ 26.55000
Stock 6610Can Ship Immediately
$ 29.5
Specifications
Series: Spartan®-II
Part Status: Active
Lead Free Status / RoHS Status: --
Number of LABs/CLBs: 1176
Moisture Sensitivity Level (MSL): --
Number of Logic Elements/Cells: 5292
Total RAM Bits: 57344
Number of I/O: 140
Voltage - Supply: 2.375 V ~ 2.625 V
Mounting Type: Surface Mount
Number of Gates: 200000
Operating Temperature: 0°C ~ 85°C (TJ)
Package / Case: 208-BFQFP
Supplier Device Package: 208-PQFP (28x28)
Base Part Number: XC2S200
Description

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com


1. Describe

Spartan-II series FPGAs have a programmable architecture with conventional, flexible, configurable logic blocks (CLB), an input/output block (IOB) surrounded by programmable perimeters. There are four Delay Locked Loops (DLLs), one at each corner of the chip. Two columns of block RAM are located on opposite sides of the chip, in the CLB and IOB columns. These functional elements are interconnected via a powerful and versatile routing hierarchy. Spartan-II FPGA customizes data by loading configuration into internal static memory cells. Use this method infinitely to reprogram loops. The values stored in these cells determine the logic functions and interconnects implemented in the FPGA. Configuration data can be written to the FPGA from an external serial PROM (master serial mode), or from serial, slave Parallel or boundary scan mode. Spartan-II FPGAs are typically used in high-volume applications, where a fast programmable versatility solution adds to the benefits. Spartan-II FPGAs are ideal for shortening product development cycles while providing a cost-effective solution for high volume production. Spartan-II FPGAs achieve high performance, low cost through advanced architectural operation and semiconductor technology. Spartan-II devices provide system clock frequencies up to 200 MHz. Apart from A traditional advantage solution for bulk programmable logic, Spartan-II FPGAs also provide on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock driver, programmable set and reset of all flip-flops, fast carry logic and many other features.

2. Feature

    1. Second generation ASIC replacement technology

        - Densities up to 5,292 logic cells and up to 200,000 system gates

        - Simplified functionality based on Virtex® FPGA fabric

        - Unlimited reprogrammability

        - extremely low cost

        - Cost-effective 0.18 micron process

    2. System level functionality

        - SelectRAM™ Tiered Memory:

            16-bit/LUT distributed RAM

            Configurable 4K-bit block RAM

            Fast interface to external RAM

        - Fully PCI compliant

        - Low-power segment routing architecture

        - Full readback capability for verification/observability

        - Dedicated carry logic for high-speed arithmetic

        - Efficient multiplier support

        - Cascade chain for wide input function

        - Rich register/latch with enable, set, reset functions

        - Four dedicated DLLs for advanced clock control

        - Four main low skew global clock distribution networks

        - IEEE 1149.1 Compliant Boundary Scan Logic

    3. Versatile I/Os and Packages

        - Pb-free package option

        - Low cost packages available in various densities

        - Family footprint compatibility in common packages

        - 16 high-performance interface standards

        - Hot-swappable compact PCI friendly

        - Zero hold time simplifies system timing

    4. 2.5V for core logic and 1.5V, 2.5V or 3.3V for I/O

    5. Fully supported by the powerful Xilinx® ISE® development system

        - Fully automatic mapping, place and route

3. Function Description

    1. Architecture description

        - Spartan-II array

        - input/output blocks

        - Configurable logic blocks

        - Block RAM

        - Clock Distribution: Delay Locked Loop

        - Boundary scan

    2. development system

    3. Configuration

        - Configure timing

    4. Design Considerations

4. DC and Switching Characteristics

    1. DC Specifications

        - Absolute Maximum Ratings

        - Recommended working conditions

        - DC characteristics

        - Boot requirements

        - DC input and output levels

    2. Switching characteristics

        - pin-to-pin parameters

        - IOB switch characteristics

        - Clock distribution characteristics

        - DLL timing parameters

        - CLB switching characteristics

        - Block RAM switching characteristics

        - TBUF switching characteristics

        - JTAG switch characteristics


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