What role can the clock play in FPGA design?
The clock is the most important signal in the FPGA design. Most of the devices in the FPGA system operate on the rising or falling edge of the clock. The setup time and hold time (hold TIme) are mentioned either in the input, output, or between the register and the register, as long as the sample is sampled to the rising or falling edge of the clock.
The settling time (Tsu:set up TIme) refers to the time required for the data to be unstable from stable to stable before the arrival of the clock edge. If the established time does not meet the requirements, the data will not be stably driven into the trigger on the rising edge of this clock. The hold time (Th: hold TIme) refers to the time after the data is stable. If the hold time does not meet the requirements, the data cannot be stably entered into the trigger. The two indicators of setup time and hold time indicate that the device itself is not ideal (sometimes extended), and it is this undesirable feature that limits the clock operating frequency of the FPGA.
First we know that setup TIme and holdup time are determined by the device, not to say that it can change as your FPGA design changes. Then, how is the FPGA clock frequency calculated? Under the condition that the clock delay jitter is not considered, the delay of a signal from the D terminal to the Q terminal of the flip-flop is assumed to be Tcd, and the delay of the combined circuit will occur after coming out from the Q terminal. Note that even if there is no combination circuit, there is a delay through the wire. This delay is called Tdelay. After this delay, the signal will go to the next trigger, and the trigger setup time tsetup must be satisfied. The clock cannot sample stable data. So these three times should add up to be smaller than the clock cycle, otherwise the data will not be able to enter the next trigger, it will enter the metastable state.
As for the relationship between the FPGA clock frequency and the holdup time, it is necessary to meet Tcd+Tdelay+TsetupTholdup when designing, that is, Tholdup determines the lower limit of the shortest path, that is, the combination logic cannot be too large or too small. This is where the hold time can work. In fact, generally can meet the retention time, generally as long as the consideration is to meet the establishment time.
A simple schematic diagram of setup time and hold time is shown in Figure 1. In Figure 1, we see that there is a dashed line before and after clk_r3, the previous dashed line (the leftmost dotted line, the left side represents the early appearance time, and the signal is simulated with modelsim) The time from the left to the right to the rising edge of clk_r3 is the settling time, and the time from the rising edge of clk_r3 to the next dotted line (the rightmost dotted line) is the hold time. As mentioned earlier in the definition of setup time and hold time, there is no data change during this time, and the data must remain stable. In this waveform, it is true that there is no change in the reg3in data during the setup and hold times, so we can stably latch the reg3in data into the reg3 output of reg3.
The waveform shown in Figure 2 below, the same signal, but we found that reg3in changed during the setup time of clk_r3, which has the consequence that the reg3in data latched by the rising edge of clk_r3 is uncertain, then the subsequent reg3out value It will also be in an indeterminate state. For example, in the first clock cycle, the original reg3in should be a stable low level, but because the delay time (Tcd+Tdelay) on the entire path is too long, the data of reg3in has not stabilized during the setup time of clk_r3. During the set-up time, the signal changes from high to low, that is, unstable state, and the consequence is that the final output of reg3out is not a certain state, it is likely to be a hypersynchronous metastable state, not The low level originally expected.
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