CPLD and FPGA
CPLD is mainly composed of programmable logic macro unit (LMC, Logic Macro Cell) around the center of programmable interconnect matrix unit, which has complex LMC logic structure and complex I/O unit interconnect structure, which can be customized by users. Generate specific circuit structures to perform certain functions. Since the internal length of the CPLD is interconnected by a fixed length of metal lines, the designed logic circuit has time predictability, which avoids the disadvantage of incomplete prediction of the segmented interconnect structure timing. By the 1990s, CPLDs had developed more rapidly, not only with electrical erasure characteristics, but also with advanced features such as edge scanning and online programming. The more commonly used are EPLD from Xilinx and CPLD from Altera.
FPGAs typically contain three types of programmable resources: programmable logic blocks, programmable I/O blocks, and programmable interconnects. Programmable logic function blocks are the basic units for implementing user functions. They are usually arranged in an array and distributed throughout the chip. The programmable I/O blocks complete the interface between the on-chip logic and the external package pins, often arranged around the array around the chip. Programmable internal interconnects include various lengths of wire segments and programmable connection switches that connect individual programmable logic blocks or I/O blocks to form a specific function circuit. FPGAs produced by different manufacturers have large differences in the size of programmable logic blocks, the structure of internal interconnects, and the use of programmable components. More commonly used FPGAs from Altera, Xinlinx and Actel. FPGAs are typically used for logic simulation. A circuit design engineer designs a circuit that first determines the line and then performs software simulation and optimization to confirm the function and performance of the designed circuit. However, as the circuit scale continues to increase and the operating frequency continues to increase, many influences on the distributed parameters will be introduced into the circuit. These effects are difficult to reflect by the software simulation method, so it is necessary to do hardware simulation. The FPGA can implement hardware simulation to make a model machine. After the software-simulated line is processed and downloaded to the FPGA, a model machine can be easily obtained. From the model machine, the designer can intuitively test its logic function and performance index.
FPGA : AT94S10AL-25BQU