What are the FPGA applications in aerospace?
Reliability design of FPGA In aerospace and space electronic equipment, FPGA is mainly used to replace standard logic, but also used in SOC technology to provide embedded microprocessor, memory, controller, communication interface, etc. Among them, reliability is the main requirement of FPGA design.
According to different functions and their importance, space electronic system design is divided into two categories: critical and non-critical. Spacecraft control is the critical category, and scientific instruments are the non-critical category. General requirements of FPGA for spacecraft control system: high reliability, radiation hardening and fail-safe. The design requirements of scientific instruments for FPGAs are generally high performance, radiation resistance and fail-safe. Its reliability is determined by performance requirements. The requirements for FPGAs also vary from system to system, such as measurement resolution, bandwidth, high-speed storage, and fault tolerance. Ability etc.
The reliability design of FPGA for aerospace is mainly realized through the hardware design and software design of the device itself.
1.FPGA
'S hardware reliability design FPGA's hardware reliability design is mainly aimed at the influence of space radiation effects, and with the help of manufacturing process and design technology, the problem of single event effect protection is solved more thoroughly. The design is generally carried out from the following aspects: FPGA overall design reinforcement, internal design of self-checking modules for indirect detection of radiation effects, and introduction of external high-reliability monitoring modules.
The overall reinforcement design refers to the use of a certain thickness of material on the outside of the electronic device for overall radiation shielding to reduce the radiation effect of the device. The materials often used are aluminum, tantalum and lipid compounds. This method is widely used in aerospace electronic components and is relatively mature. For example, Honeywell, as a major supplier of US military microelectronic products, has a wide coverage of reinforced ASIC technology. Aeroflex adopts the method of "design ruggedized, commercial IC process line streaming" to provide advanced performance rugged ASIC products, and has the ability to develop digital-analog hybrid rugged ASICs. This technical circuit that uses commercial lines to stream chips to produce military and reinforced microelectronic products is not only conducive to getting rid of the constraints of process reinforcement on device development, but also conducive to meeting users' needs for advanced reinforcement devices, reducing costs and shortening delivery time.
Atmel provides users with high-performance, small-size, and low-power device process resources, including radiation-resistant, high-speed, low-power, digital-analog hybrid CMOS technology for aerospace, and CMOS technology with embedded EEPROM. There are many domestic units engaged in the development of military microelectronic devices, including state-owned scientific research units and non-state-owned IC development companies. However, there are not many units that can complete the development of radiation-resistant hardened ICs. The domestically developed ruggedized ASIC products have been successfully applied in satellites.
The use of bulk silicon epitaxial layer can also prevent SEI from occurring. For example, Xilinx's virtex-II radiation tolerant products are based on military-grade devices and further adopt an epitaxial substrate design, and their ability to resist total dose ionization effects is tested in accordance with MIL-STD-883 Method 1019. The purpose of the self-check module is to predict the normal operation of the entire FPGA through the normal operation of certain modules. The self-inspection module is implemented by simple logic circuits distributed near important wiring areas of the FPGA, and can also be directly output by the voting results of the multi-mode redundant module or the remainder detection method and the parity check method.
4.2 FPGA software reliability design aerospace applications
FPGA software reliability design refers to the application of software program configuration to shield the malfunction caused by radiation effects. Among them, the redundant design method is recognized as a more reliable method to deal with radiation effects. Commonly used redundancy designs include three-module redundancy (TMR, Triplemodule redundancy) and partial three-module redundancy (PTMR, ParTIaltriple module redundancy). Although TMR can improve the reliability of the system, it will also reduce the speed of the module, occupy resources and increase power. Comprehensive consideration of other design indicators, the partial three-mode redundancy method can be used for key parts according to actual conditions.
Although the redundant structure can guarantee the reliability of the system, it cannot detect and correct errors in time, or introduce too much combinational logic to find the errors. When applied to FPGA, it increases the possibility of errors in the fault-tolerant circuit itself. In addition, the unattended operation characteristics of the spaceborne system make system reconstruction and failure recovery very difficult.
The read-back check and reconfiguration (or partial reconfiguration) of the configuration memory is an effective method to resist radiation effects. Reloading part of the configuration can repair the impact of the SEU effect, and its frequency should be the worst case. 10 times the incidence of SEU effect. In the reloading logic design, the implementation of reloading and the loading content need to be carefully designed. Not all content can be reloaded, and not all content needs to be reconfigured.
In the system design, the high-reliability anti-fuse FPGA is used to read the configuration data of the Xilinx FPGA from the non-volatile mass memory to configure it. During operation, the configuration memory that is most susceptible to radiation effects is read in columns, and then compared with standard data, and the columns with errors are partially reconfigured.
The programmable IO of FPGA is also susceptible to the influence of radiation particles to produce SEU and SEL. It is a very effective method to design the three-mode redundancy design method for the input and output pins, but this method will require 3 times the I/O resources. If SET acts on the clock circuit or other data and control lines, it is easy to produce short pulse jitter, which may cause false triggering of the circuit or data latch errors. In the design, synchronous reset can be used to design the internal reset circuit and control line enable The signal line and logic data should match the enable signal as much as possible when latching.
If you want to know more, our website has product specifications for FPGA applications, you can go to ALLICDATA ELECTRONICS LIMITED to get more information