CDCE62002RHBR

The CDCE62002RHBR device is a single-chip clock generator, phase-locked loop (PLL) and frequency synthesizer for communication interface applications. It combines several clock and PLL functions into one device, including oscillator, oscillator buffer, PLL synthesizer core and output buffers.

The CDCE62002RHBR was specifically designed for applications in Clock and Data Communications (C&D) such as telecom and digital audio/video interfaces. These applications require high performance and accuracy of clocks, as well as PLL tuning to achieve precise frequency translation or frequency multiplication.

It operates either as a fixed frequency oscillator (FXO) or as a 3V to 3.3V PLL. The CDCE62002RHBR provides differential LVPECL clock I/O with sweeping frequencies up to 622 MHz. The output frequency range is adjustable from 19.44 MHz to 622 MHz, with jitter performance down to 72 ps peak-to-peak.

The CDCE62002RHBR also has an integrated differential line receiver Amplify-and-Waveform Correction (AWC) preamplifier. The AWC was designed to allow the device to recover serial data signals operating at frequencies up to 622 MHz, while suppressing any false triggering or erroneous signals due to noise and other sources. The AWC\'s adjustable gain block allows for fine-tuning of the input volume, as well as the frequency response of the system.

CDCE62002RHBR offers two different core architectures, either a single DLL-based or a multi-DLL-based. The multi-DLL architecture enables the user to increase the frequency synthesis capability by combining multiple DLLs, each running at different frequencies. The single DLL is designed to synthesize frequency above 105 MHz, while the multi-DLL architecture can be used to synthesize frequencies up to 622 MHz.

The device also has integrated programmable PLLs that enable closed-loop control of the output frequency. The PLLs on the CDCE62002RHBR have programmable frequency dividers and reference dividers, as well as output dividers to allow for the generation of multiple frequencies from one input clock. The programmable dividers enable the user to adjust the output frequency to match desired application requirements.

Additionally, the device also includes integrated charge pump and loop filters to reduce noise and jitter. The proprietary charge pump design, along with a wide loop bandwidth, helps the device to achieve excellent jitter performance down to 72 ps peak-to-peak, while still allowing the user to select a wide range of operating frequencies. The programmable loop filter also enables the user to select the optimal damping factor to meet different application requirements.

The CDCE62002RHBR provides two different operating modes: an open-loop, or closed-loop. In open-loop mode, the device will generate an output frequency that is determined by the input reference frequency and the selected dividers. In closed-loop mode, the device will use an external reference clock in combination with the selected dividers in order to generate an output frequency that is locked to the reference frequency.

In summary, the CDCE62002RHBR is a high-performance clock generator, PLL and frequency synthesizer designed for clock and data communications applications. It features programmable frequency synthesis capability that allows the device to achieve high accuracy and jitter performance, while still providing a wide range of output frequencies. The AWC preamplifier, integrated charge pump and loop filters allow the device to recover data signals and reduce noise and jitter.