DS92LX1621SQE/NOPB Integrated Circuits (ICs)

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DS92LX1621SQE/NOPB Serializers, Deserializers Application Field and Working Principle

The DS92LX1621SQE/NOPB serializer/deserializer is a low-power, low-latency, full-featured CMOS IC designed for transmitting data up to 16 Gbps over copper or fiber optic cables. This device includes a transmitter functional formatter and a compatible receiver phase locked loop (PLL) serializer/deserializer. The transmitter and receiver use an adaptive equalizer design provided by the on-chip Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) to improve the SNR to compensate for signal distortion due to the attenuation, crosstalk, and skew over long transmission lines. The serializer/deserializer supports seria data rates up to 16 Gbps.

Application Field

The DS92LX1621SQE/NOPB is a serializer/deserializer that is ideal for high-performance computing applications, such as connected storage, graphics, gaming and graphics cards, ultra-high definition video and networking equipment. The serializer/deserializer supports multi-lane data transmission, each with data rates up to 16 Gbps.

The device features low-latency output, making it well suited for high performance industrial applications that require data to be received and sent quickly, such as factory automation, robotics, image processing and the Internet of Things (IoT).

The device is also suited for medical instrumentation applications, such as patient monitoring and medical imaging, due to its low input voltage and power consumption.

Working Principle

The DS92LX1621SQE/NOPB has a transmitter section and a receiver section. The transmitter section includes a formatter, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and an ECU (Equalizing and Clock Recovery Unit). The formatter synchronizes the incoming data stream and adds control logic bits. It then converts the data into a differential serial signal that is sent to the ECU.

The ECU is responsible for equalizing the signal to overcome cable attenuation, jitter, crosstalk and skew. The ECU and DAC then combine the equalized signal and an externally-supplied reference clock to regenerate a modulated signal, which is sent to the external system clock and data lines.

The receiver section of the DS92LX1621SQE/NOPB contains a programmable phase-locked loop (PLL) and a low-noise amplifier (LNA). The LNA amplifies the received signal, which is then sent to the PLL. The PLL regenerates the reference clock and synchronizes the incoming data stream. The data stream is then sent to the formatter, which separates the data and control bits, and reconstructs the original data stream.

The DS92LX1621SQE/NOPB also contains an asynchronous FIFO that allows it to store data until the processor is available to process it. The FIFO also reduces latency by allowing data to be stored while the processor is busy processing other data.

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