Allicdata Part #: | IS62LV256AL-20TLI-ND |
Manufacturer Part#: |
IS62LV256AL-20TLI |
Price: | $ 0.77 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | ISSI, Integrated Silicon Solution Inc |
Short Description: | IC SRAM 256K PARALLEL 28TSOP I |
More Detail: | SRAM - Asynchronous Memory IC 256Kb (32K x 8) Para... |
DataSheet: | IS62LV256AL-20TLI Datasheet/PDF |
Quantity: | 1000 |
936 +: | $ 0.70086 |
Series: | -- |
Packaging: | Tray |
Part Status: | Active |
Memory Type: | Volatile |
Memory Format: | SRAM |
Technology: | SRAM - Asynchronous |
Memory Size: | 256Kb (32K x 8) |
Write Cycle Time - Word, Page: | 20ns |
Access Time: | 20ns |
Memory Interface: | Parallel |
Voltage - Supply: | 3 V ~ 3.6 V |
Operating Temperature: | -40°C ~ 85°C (TA) |
Mounting Type: | Surface Mount |
Package / Case: | 28-TSSOP (0.465", 11.80mm Width) |
Supplier Device Package: | 28-TSOP I |
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The IS62LV256AL-20TLI from ISSI is a high-speed CMOS SRAM memory device. It consists of 256K x 8-Bit of SRAM and is organized as 32K words x 8-Bit. This device is ideal for built-in cache, packet buffer and hot-swap applications in card-based systems or embedded applications. The IS62LV256AL-20TLI is available in a JEDEC standard TSOP II-44 package and operates as low as 2.7V.
The main application fields for IS62LV256AL-20TLI SRAM include full-speed lookup tables,FIFOs, industrial control process image memory, animation memories and communications packet buffering. The key features of this device include low-voltage operation, high-speed access time, improved noise margin and fast read/write cycle time. Additionally, it offers improved stand-by current, high-reliability down to 8V voltage and better data integrity.
The working principle of the IS62LV256AL-20TLI SRAM is based on a register design logic that stores a gate array structure in the integrated circuit. This structure is powered up by two power supply pins that are connected between on chip supply and ground level. The logic uses the on-chip internal supply to generate the complementary clock signal when slave read and write is enabled. The output of this clock will determine the location of the data to be read or stored.
The device also includes an address counter that keeps track of where the data is stored. The address counter will increment every time the READ or WRITE command is executed and the value of the counter is controlled by the Clock input of the device. The output of the device is controlled by a data line that transmits a 8-bit data from the appropriate address location.
Once the data is stored it can be read by maintaining the device in the read state. The output will be followed by a small initialization delay to suit the speed requirements of the device. The device can also be placed in the write state, enabling the data to be stored at the selected address locations. Once the data is stored, it can again be checked by placing the device in the read state.
The IS62LV256AL-20TLI SRAM offers better performance, improved noise margin and better data integrity than most SRAMs on the market. It offers a low-voltage operation with a high read and write speed, making it an ideal choice for embedded applications and card-based systems. With its improved stand-by current and improved noise margin, it is ideal for full-speed lookup tables and animation memories.
The specific data is subject to PDF, and the above content is for reference
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IS62C256AL-45TLI | ISSI, Integr... | -- | 1829 | IC SRAM 256K PARALLEL 28T... |
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