MCF5282CVM66

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1. Feature

    1. Static version 2 ColdFire variable-length RISC processor

    2. System debugging support

    3. On-chip memory

    4. Energy management

    5. Fast Ethernet Controller (FEC)

    6. FlexCAN 2.0B module

    7. Three Universal Asynchronous/Synchronous Receiver Transmitters (UARTs)

    8. I2C module

    9. Queued Serial Peripheral Interface (QSPI)

  10. Queued Analog-to-Digital Converter (QADC)

  11. Four 32-bit DMA timers

  12. Two 4-channel general-purpose timers

  13. Four Periodic Interrupt Timers (PITs)

  14. Software Watchdog Timer

  15. Phase-locked loops (PLLs)

  16. Two interrupt controllers

  17. DMA controller

  18. External bus interface

  19. Chip Integrated Module (CIM)

  20. General purpose input/output interface

  21. JTAG support for system-level board testing

2. Describe

The processor core consists of two independent pipelines, which are decoupled by instruction buffers. this A two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction address generation and instruction bring it. The instruction buffer is a first-in-first-out (FIFO) buffer that holds pending prefetched instructions Executes in the Operand Execution Pipeline (OEP). OEP consists of two pipeline stages. The first stage Decode instruction and select operand (DSOC); second stage (AGEX) execute instruction Executes and computes operand effective addresses, if necessary. The V2 core implements the ColdFire instruction set architecture revision A, which adds support for Separate user stack pointer register and four new instructions to assist bit manipulation. also, The MCF5282 core includes an Enhanced Multiply Accumulate Unit (EMAC) for improved signal processing ability. The EMAC implements a 4-stage execution pipeline optimized for 32 x 32-bit operations, Four 48-bit accumulators are supported. Supported operands include 16-bit and 32-bit signed and unsigned Integer, signed fractional operands, and a complete instruction set for handling these data types. this EMAC provides excellent support for performing DSP operations in a single processor environment at the lowest hardware cost.

3. Debug module

Provides ColdFire processor core debug interface to support system debug in conjunction with Low-cost debugging and emulator development tools. Through the standard debug interface, users can access Live trace and debug information. This allows full speed debugging of processors and system No need for expensive in-circuit emulators. The debug interface is a superset of the BDM interface Available on Freescale's 683xx series of parts. On-chip breakpoint resources include a total of 6 programmable registers—a set of address registers (with two 32-bit registers) a set of data registers (with one 32-bit data register plus a 32-bit data mask register) and a 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed by Dedicated debug serial communication channel or supervisor mode programming from processor Model. The breakpoint register can be configured as a combination of address, data and PC conditions with various single-level or two-level definitions. Trigger events can be programmed as Generate a processor halt or start debug interrupt exception. To support program trace, the version 2 debug module provides processor status (PST[3:0]) and debug Data (DDATA[3:0]) port. These buses and the CLKOUT output provide execution status, capture Operand data and branch target addresses define the processor's dynamic execution path The clock frequency of the CPU.