MKE02Z64VLD4

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1. Feature

    1. Operating characteristics

        – Voltage range: 2.7 to 5.5 V

        – Flash write voltage range: 2.7 to 5.5 V

        – Temperature range (ambient): -40 to 105°C

    2. Performance

        – Up to 40 MHz Arm® Cortex-M0+ core and up to 20 MHz bus clock

        – Single cycle 32-bit x 32-bit multiplier

        – Single-cycle I/O access port

    3. Memory and memory interfaces

        – Flash memory up to 64 KB

        – EEPROM up to 256 B

        – Up to 4 KB RAM

    4. Bell

        – Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 20 MHz crystal or ceramic resonator; select low power or high gain oscillator

        – Internal Clock Source (ICS) - Internal FLL with internal or external reference, 31.25 kHz prescaled internal reference for 32 MHz system clock

        – Internal 1 kHz Low Power Oscillator (LPO)

    5. System peripherals

        – Power Management Module (PMC) with three power supplies Modes: run, wait, stop

        – Low Voltage Detection (LVD) with reset or interrupt, Alternative itinerary

        – Watchdog (WDOG) with independent clock source

        – Programmable cyclic redundancy check module (CRC)

        – Serial Wire Debug Interface (SWD)

        – Bit Manipulation Engine (BME)

    6. Security and Integrity Module

        – 64-bit unique identification (ID) number for each chip

    7. Human-Machine Interface

        – Up to 57 general purpose input/output (GPIO)

        – Two keyboard interrupt modules (KBI) up to 8 bits

        – External Interrupt (IRQ)

    8. Analog module

        – One 12-bit SAR ADC, up to 16 channels, in Stop mode, optional hardware trigger (ADC)

        – Two analog comparators including a 6-bit DAC and programmable reference input (ACMP)

    9. Timer

        – One 6-channel FlexTimer/PWM (FTM)

        – Two 2-channel FlexTimer/PWM (FTM)

        – A 2-channel Periodic Interrupt Timer (PIT)

        – Real Time Clock (RTC)

  10. Communication Interface

        – Two SPI modules (SPI)

        – Up to three UART modules (UART)

        – One I2C module (I2C)

  11. Package options

        – 64-pin QFP/LQFP

        – 44-pin LQFP

        – 32-pin LQFP

        – 32-pin QFN

2. Pin configuration

3. Electromagnetic Compatibility

Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU is located. Board design and layout, circuit topology selection, location and characterization of external components, and MCU software Operation plays an important role in EMC performance. System designers must review the following application notes available on nxp.com for advice and guidance specific to optimizing EMC performance.

    1. AN2321: Board Level Electromagnetic Compatibility Design

    2. AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers

    3. AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers

    4. AN2764: Improving Transient Immunity for Microcontroller-Based Applications

    5. AN1259: System Design and Layout Techniques for Noise Reduction in MCU-Based Systems

4. FTM Module Timing

The synchronizer circuit determines the shortest identifiable input pulse or the fastest clock that can be used as an optional external source for the timer counter. These synchronizers operate according to the current bus rate clock.

5. Thermal characteristics

This section provides information on operating temperature range, power dissipation, and package thermal resistance. The power dissipation on the I/O pins is typically small compared to the power dissipation in the on-chip logic and voltage regulator circuits, and is determined by the user rather than controlled by the MCU design. To account for PI/O in power calculations, determine the difference between the actual pin voltage and VSS or VDD, then multiply by the pin current for each I/O pin. The difference between the pin voltage and VSS or VDD will be very small, except in the case of unusually high pin currents (heavy loads).

6. SPI Switch Specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master-slave operation. Many transport properties are programmable. The following table provides the timing characteristics of the classic SPI timing mode. All timings are shown relative to 20% VDD and 80% VDD and a 25 pF load on all SPI pins unless otherwise noted. All timings assume high drive strength is enabled for the SPI output pins

7. Signal multiplexing and pin assignment

The following table shows the signals available on each pin and the location of these pins on the devices supported by this document. The port control block is responsible for selecting the ALT functions available on each pin.