S9S12GN32AMLF

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1. Describe

The S9S12GN32AMLF family is a family of automotive 16-bit microcontrollers designed for Low cost, high performance and low pin count. This family is designed to bridge high-end 8-bit Microcontrollers and high-performance 16-bit microcontrollers such as the MC9S12XS family. This The MC9S12G family targets general-purpose automotive applications requiring CAN or LIN/J2602 communication. Typical examples of these applications include body controllers, occupant detection, door Modules, Seat Controllers, RKE Receivers, Smart Actuators, Lighting Modules and Smart Junction Boxes. The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, including error-correcting code (ECC) on flash memory, fast analog-to-digital converter (ADC) and Frequency Modulated Phase Locked Loop (IPLL) for improved EMC performance. The MC9S12G family is optimized for smaller program memory down to 16k. To simplify customer use, it has a 4-byte erasable sector size EEPROM. The MC9S12G family offers all the benefits and efficiencies of a 16-bit MCU while maintaining the cost, power, EMC and code size efficiency benefits that low NXP users currently enjoy over existing 8- and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family runs in 16-bit without waiting for extensive access to all peripherals and memory. The MC9S12G family is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP, and 20-pin TSSOP package options, and Designed to maximize feature count, especially for low pin count packages. In addition to the I/O ports available in each module, more I/O ports are interrupt capable, allowing Wake from stop or wait mode.

2. Features

    1. S12 CPU core

    2. Up to 240 Kbyte on-chip flash with ECC

    3. Up to 4 Kbyte EEPROM with ECC

    4. Up to 11 Kbyte on-chip SRAM

    5. Phase locked loop (IPLL) frequency multiplier with internal filter

    6. 4–16 MHz amplitude controlled Pierce oscillator

    7. 1 MHz internal RC oscillator

    8. Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture, output compare, counter, and pulse accumulator functions

    9. Pulse width modulation (PWM) module with up to eight x 8-bit channels

  10. Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter (ADC)

  11. Up to two 8-bit digital-to-analog converters (DAC)

  12. Up to one 5V analog comparator (ACMP)

  13. Up to three serial peripheral interface (SPI) modules

  14. Up to three serial communication interface (SCI) modules supporting LIN communications

  15. Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)

  16. On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

  17. Autonomous periodic interrupt (API)

  18. Precision fixed voltage reference for ADC conversions

  19. Optional reference voltage attenuator module to increase ADC accuracy

3. Pin configuration

4. 16-Bit Central Processor Unit (CPU)

    1. Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution

    2. Includes many single-byte instructions. This allows much more efficient use of ROM space.

    3. Extensive set of indexed addressing capabilities, including:

        - Using the stack pointer as an indexing register in all indexed operations

        - Using the program counter as an indexing register in all but auto increment/decrement mode

        - Accumulator offsets using A, B, or D accumulators

        - Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)

5. On-Chip Flash with ECC

    1. Up to 240 Kbyte of program flash memory

        - 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection

        - Erase sector size 512 bytes

        - Automated program and erase algorithm

        - User margin level setting for reads

        - Protection scheme to prevent accidental program or erase

    2. Up to 4 Kbyte EEPROM

        - 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection

        - Erase sector size 4 bytes

        - Automated program and erase algorithm

        - User margin level setting for reads

6. Port Integration Module (PIM)

    1. Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O

    2. Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis

    3. Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin

    4. Control registers to enable/disable open-drain (wired-or) mode on ports S and M

    5. Interrupt flag register for pin interrupts on ports P, J and AD

    6. Control register to configure IRQ pin operation

    7. Routing register to support programmable signal redirection in 20 TSSOP only

    8. Routing register to support programmable signal redirection in 100 LQFP package only

    9. Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram rouf API_EXTCLK in all packages.

  10. Control register for free-running clock outputs

7. System Integrity Support

    1. Power-on reset (POR)

    2. System reset generation

    3. Illegal address detection with reset

    4. Low-voltage detection with interrupt or reset

    5. Real time interrupt (RTI)

    6. Computer operating properly (COP) watchdog

        - Configurable as window COP for enhanced failure detection

        - Initialized out of reset using option bits located in flash memory

    7. Clock monitor supervising the correct function of the oscillator

8. Controller Area Network Module (MSCAN)

    1. 1 Mbit per second, CAN 2.0 A, B software compatible

        - Standard and extended data frames

        - 0–8 bytes data length

        - Programmable bit rate up to 1 Mbps

    2. Five receive buffers with FIFO storage scheme

    3. Three transmit buffers with internal prioritization

    4. Flexible identifier acceptance filter programmable as:

        - 2 x 32-bit

        - 4 x 16-bit

        - 8 x 8-bit

    5. Wakeup with integrated low pass filter option

    6. Loop back for self test

    7. Listen-only mode to monitor CAN bus

    8. Bus-off recovery by software intervention or automatically

    9. 16-bit time stamp of transmitted/received messages

9. Serial Communication Interface Module (SCI)

    1. Up to three SCI modules

    2. Full-duplex or single-wire operation

    3. Standard mark/space non-return-to-zero (NRZ) format

    4. Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

    5. 13-bit baud rate selection

    6. Programmable character length

    7. Programmable polarity for transmitter and receiver

    8. Active edge receive wakeup

    9. Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602

10. Serial Peripheral Interface Module (SPI)

    1. Up to three SPI modules

    2. Configurable 8- or 16-bit data size

    3. Full-duplex or single-wire bidirectional

    4. Double-buffered transmit and receive

    5. Master or slave mode

    6. MSB-first or LSB-first shifting

    7. Serial clock phase and polarity options