T1042NXE7WQB

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1. Describe

The T1042NXE7WQB advanced multi-core processor combines high-performance data Path acceleration required by the network and network and peripheral bus interfaces, Telecom/datacom, wireless infrastructure and military/aerospace applications. The chip can be used for combined control, data path and application layer processing Routers, switches, gateways, and general embedded computing systems. its high Integration provides significant performance advantages over multiple discrete components device while also simplifying board design. 

2. Feature

    1. e5500 core built on Power Architecture® technology,

        – T1042 has four cores and T1022 has two cores

        – Each core has a private 256KB L2 cache

    2. 256 KB shared L3 CoreNet Platform Cache (CPC)

    3. Hierarchical interconnect structure

        – CoreNet Coherency Manager supports coherent and non-coherent transactions for prioritization and bandwidth allocation between CoreNet endpoints

        – 150Gbps coherent read bandwidth

    4. A 32-bit/64-bit DDR3L/DDR4 SDRAM memory controller

        – ECC and interleaving support

    5. Data Path Acceleration Architecture (DPAA) includes acceleration of the following functions:

        – Packet parsing, classification and distribution

        – Queue management for scheduling, packet sequencing and congestion management

        – Hardware buffer management for buffer allocation and deallocation

        – Encryption acceleration

        – RegEx pattern matching acceleration

        – IEEE Std 1588™ support

    6. Parallel Ethernet interface

        – Up to two RGMII interfaces

        – One MII interface

    7. Eight SerDes lanes for high-speed peripheral interface

        – Four PCI Express 2.0 controllers

        – Two Serial ATA (SATA 3Gb/s) controllers

        – Up to five SGMII interfaces supporting 1000 Mbps

        – Up to two SGMII interfaces, up to 2500 Mbps

        – Support 1000Base-KX

    8. Additional peripheral interfaces

        – Two Hi-Speed USB 2.0 controllers with integrated PHY

        – Enhanced Secure Digital Host Controller with Mass Storage Card Support (SD/eSDHC/eMMC)

        – Enhanced Serial Peripheral Interface (eSPI)

        – Four I2C controllers

        – Two DUARTs

        – Integrated Flash Controller Supporting NAND and NOR Flash

        – Display Interface Unit (DIU) with 12-bit Double Data Rate

        – Time division multiplexing interface

        – Four GPIO controllers support up to 109 general-purpose I/O signals

        – Two 8-channel DMA engines 

        – Multicore Programmable Interrupt Controller (MPIC)

    9. QUICC engine block

        – 32-bit RISC controller for flexible support of communication peripherals

        – Serial DMA channel for receive and transmit on all serial channels 

        – Two general-purpose communications controllers supporting TDM, HDLC, and UART

  10. 780 FC-PBGA package, 23mm x 23mm