TPS51200DRCR Integrated Circuits (ICs)

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1. Description

The TPS51200DRCR device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration. The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 μF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications. The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

2. Features

    1. Input Voltage: Supports 2.5-V Rail and 3.3-V Rail

    2. VLDOIN Voltage Range: 1.1 V to 3.5 V

    3. Sink and Source Termination Regulator Includes Droop Compensation

    3. Requires Minimum Output Capacitance of 20-μF (Typically 3 × 10-μF MLCCs) for Memory Termination Applications (DDR)

    4. PGOOD to Monitor Output Regulation

    5. EN Input

    6. REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider

    7. Remote Sensing (VOSNS)

    8. ±10-mA Buffered Reference (REFOUT)

    9. Built-in Soft Start, UVLO, and OCL

  10. Thermal Shutdown

  11. Supports DDR, DDR2, DDR3, DDR3L, LowPower DDR3, and DDR4 VTT Applications

  12. 10-Pin VSON Package With Thermal Pad

3. Applications

    1. Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4

    2. Notebooks, Desktops, and Servers

    3. Telecom and Datacom

    4. Base Stations

    5. LCD-TVs and PDP-TVs

    6. Copiers and Printers

    7. Set-Top Boxes

4. Pin Configuration

5. Pin Functions

6. Feature Description

1. Sink and Source Regulator

The TPS51200 is a sink and source tracking termination regulator specifically designed for low input voltage, low-cost, and low external component count systems where space is a key application parameter. The device integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, connect a remote sensing terminal, VOSNS, to the positive terminal of each output capacitor as a separate trace from the high current path from VO.

2. Reference Input

The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The TPS51200 device supports REFIN voltages from 0.5 V to 1.8 V, making it versatile and ideal for many types of low-power LDO applications.

3. Reference Output

When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT becomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT is less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-kΩ MOSFET. REFOUT is independent of the EN pin state.

4. Soft-Start Sequencing

A current clamp implements the soft-start function of the VO pin. The current clamp allows the output capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL) level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. The soft-start function is completely symmetrical and the overcurrent limit works for both directions. The soft-start function works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage.

5. Enable Control

When EN is driven high, the VO regulator begins normal operation. When the device drives EN low, VO discharges to GND through an internal 18-Ω MOSFET. REFOUT remains on when the device drives EN low. Ensure that the EN pin voltage remains lower than or equal to VVIN at all times.

6. Powergood Function

The TPS51200 device provides an open-drain PGOOD output that goes high when the VO output is within ±20% of REFOUT. PGOOD de-asserts within 10 μs after the output exceeds the size of the powergood window. During initial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD is an open-drain output, a pull-up resistor with a value between 1 kΩ and 100 kΩ, placed between PGOOD and a stable active supply voltage rail is required.

7. Current Protection

The LDO has a constant overcurrent limit (OCL). The OCL level reduces by one-half when the output voltage is not within the powergood window. This reduction is a non-latch protection.

8. UVLO Protection

For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is a non-latch protection.

9. Thermal Shutdown

The TPS51200 monitors junction temperature. If the device junction temperature exceeds the threshold value, (typically 150°C), the VO and REFOUT regulators both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection.

10. Tracking Start-up and Shutdown

The TPS51200 also supports tracking start-up and shutdown when the EN pin is tied directly to the system bus and not used to turn on or turn off the device. During tracking start-up, VO follows REFOUT once REFIN voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail through a voltage divider. The typical soft-start time (tSS) for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The soft-start time of the VO output no longer depends on the OCL setting, but it is a function of the soft-start time of the VDDQ rail. PGOOD is asserted 2 ms after VVO is within ±20% of REFOUT. During tracking shutdown, the VO pin voltage falls following REFOUT until REFOUT reaches 0.37 V. When REFOUT falls below 0.37 V, the internal discharge MOSFETs turn on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted when VO is beyond the ±20% range of REFOUT. Figure 20 shows the typical timing diagram for an application that uses tracking start-up and shutdown.

11. Output Tolerance Consideration for VTT DIMM Applications

The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 21). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 22 for typical characteristics for a single memory cell.