XCZU11EG-2FFVC1760I

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1. Description

The Zynq® UltraScale+™ MPSoC family is based on the Xilinx® UltraScale™ MPSoC architecture. This family of products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex®-A53 and dual-core Arm Cortex-R5F based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of peripheral connectivity interfaces.

2. Arm Cortex-A53 Based Application Processing Unit (APU)

    1. Quad-core or dual-core

    2. CPU frequency: Up to 1.5GHz

    3. Extendable cache coherency

    4. Armv8-A Architecture

        - 64-bit or 32-bit operating modes

        - TrustZone security

        - A64 instruction set in 64-bit mode, A32/T32 instruction set in 32-bit mode

    5. NEON Advanced SIMD media-processing engine

    6. Single/double precision Floating Point Unit (FPU)

    7. CoreSight™ and Embedded Trace Macrocell (ETM)

    8. Accelerator Coherency Port (ACP)

    9. AXI Coherency Extension (ACE)

  10. Power island gating for each processor core

  11. Timer and Interrupts

        - Arm Generic timers support

        - Two system level triple-timer counters

        - One watchdog timer

        - One global system timer

  12. Caches

        - 32KB Level 1, 2-way set-associative instruction cache with parity (independent for each CPU)

        - 32KB Level 1, 4-way set-associative data cache with ECC (independent for each CPU)

        - 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs)

3. Dual-core Arm Cortex-R5F Based Real-Time Processing Unit (RPU)

    1. CPU frequency: Up to 600MHz

    2. Armv7-R Architecture

        - A32/T32 instruction set

    3. Single/double precision Floating Point Unit (FPU)

    4. CoreSight™ and Embedded Trace Macrocell (ETM)

    5. Lock-step or independent operation

    6. Timer and Interrupts:

        - One watchdog timer

        - Two triple-timer counters

    7. Caches and Tightly Coupled Memories (TCMs)

        - 32KB Level 1, 4-way set-associative instruction and data cache with ECC (independent for each CPU)

        - 128KB TCM with ECC (independent for each CPU) that can be combined to become 256KB in lockstep mode

4. On-Chip Memory

    1. 256KB on-chip RAM (OCM) in PS with ECC

    2. Up to 36Mb on-chip RAM (UltraRAM) with ECC in PL

    3. Up to 35Mb on-chip RAM (block RAM) with ECC in PL

    4. Up to 11Mb on-chip RAM (distributed RAM) in PL

5. Arm Mali-400 Based GPU

    1. Supports OpenGL ES 1.1 and 2.0

    2. Supports OpenVG 1.1

    3. GPU frequency: Up to 667MHz

    4. Single Geometry Processor, Two Pixel Processors

    5. Pixel Fill Rate: 2 Mpixels/sec/MHz

    6. Triangle Rate: 0.11 Mtriangles/sec/MHz

    7. 64KB L2 Cache

    8. Power island gating 

6. Dedicated I/O Peripherals and Interfaces

    1. PCI Express — Compliant with PCIe® 2.1 base specification

        - Root complex and End Point configurations

        - x1, x2, and x4 at Gen1 or Gen2 rates

    2. SATA Host

        - 1.5, 3.0, and 6.0Gb/s data rates as defined by SATA Specification, revision 3.1

        - Supports up to two channels

    3. DisplayPort Controller

        - Up to 5.4Gb/s rate

        - Up to two TX lanes (no RX support)

    4. Four 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support

        - Scatter-gather DMA capability

        - Recognition of IEEE Std 1588 rev.2 PTP frames

        - GMII, RGMII, and SGMII interfaces

        - Jumbo frames

    5. Two USB 3.0/2.0 Device, Host, or OTG peripherals, each supporting up to 12 endpoints

        - USB 3.0/2.0 compliant device IP core

        - Super-speed, high- speed, full-speed, and low-speed modes

        - Intel XHCI- compliant USB host

    6. Two full CAN 2.0B-compliant CAN bus interfaces

        - CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant

    7. Two SD/SDIO 2.0/eMMC4.51 compliant controllers

    8. Two full-duplex SPI ports with three peripheral chip selects

    9. Two high-speed UARTs (up to 1Mb/s)

  10. Two master and slave I2C interfaces

  11. Up to 78 flexible multiplexed I/O (MIO) (up to three banks of 26 I/Os) for peripheral pin assignment

  12. Up to 96 EMIOs (up to three banks of 32 I/Os) connected to the PL