ATSAML21J17B-AUT

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1. Description

Atmel® SMART ATSAML21J17B-AUT is a series of ultra low-power microcontrollers using the 32-bit Arm® Cortex®-M0+ processor, and ranging from 32-pin to 64-pin with up to 256 KB Flash and 40 KB of SRAM. The SAM L21 devices operate at a maximum frequency of 48 MHz and reach 2.46 CoreMark®/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The Atmel SAM L21 devices provide the following features: In-system programmable Flash, 16-channel direct memory access (DMA) controller, 12-channel Event System, programmable interrupt controller, up to 51 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and three Timer/ Counters for Control (TCC) where each TC/TCC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8-bit or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting, and other control applications. Two TCC can operate in 24-bit mode, the third TCC can operate in 16-bit mode. The series provide one full-speed USB 2.0 embedded host and device interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up to 3.4 MHz, SMBus, PMBus, and LIN slave; up to twenty channel 1 MSPS 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, two 12-bit 1 MSPS DACs, two analog comparators with window mode, three independent cascadable OPAMPs supporting internal connection with others analog features, Peripheral Touch Controller supporting up to 192 buttons, sliders, wheels and proximity sensing; programmable Watchdog Timer (WDT), Brown-out Detector (BOD) and Power-on Reset (POR) and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM L21 devices have four software-selectable sleep modes: Idle, Stand-by, Backup and Off. In Idle mode the CPU is stopped while all other functions can be kept running. In Stand-by mode all clocks and functions are stopped except those selected to continue running. In this mode all RAMs and logic contents are retained. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows some internal operation like DMA transfer and the CPU to wake up only when needed, for example, when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react, and send events even in Stand-by mode. The SAM L21 devices have two software-selectable performance levels (PL0 and PL2) allowing the user to scale the lowest core voltage level that will support the operating frequency. To further minimize consumption, specifically leakage dissipation, the SAM L21 devices utilizes power domain gating technique with retention to turn off some logic area while keeping its logic state. This technique is fully handled by hardware. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debugging of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The Atmel SAM L21 devices are supported with a full suite of programs and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits.

2. Features

    1. Processo

        – Arm Cortex-M0+ CPU running at up to 48 MHz

    2. Single-cycle hardware multiplier

    3. Micro Trace Buffer

    4. Memories

         – 32/64/128/256-KB in-system self-programmable Flash

         – 1/2/4/8-KB Flash Read-While-Write section

         – 4/8/16/32-KB SRAM main memory

         – 2/4/8/8-KB SRAM low-power memory

    5. System

        – Power-on Reset (POR) and Brown-out Detection (BOD)

        – Internal and external clock options

        – External Interrupt Controller (EIC)

        – 16 external interrupts

        – One non-maskable interrupt

        – Two-pin Serial Wire Debug (SWD) programming, testing, and debugging interface

    6. Low Power

        – Idle, Stand-by, Backup, and Off Sleep modes

        – SleepWalking peripherals

        – Static and Dynamic Power Gating Architecture

        – Battery backup support

        – Two performance levels

        – Embedded Buck/LDO regulator supporting on-the-fly selection

    7. Peripherals

        – 16-channel Direct Memory Access Controller (DMAC)

        – 12-channel Event System

        – Up to five 16-bit Timer/Counters (TC) including one low-power TC, each configurable as:

    8. 16-bit TC with two compare/capture channels

    9. 8-bit TC with two compare/capture channels

  10. 32-bit TC with two compare/capture channels, by using two TCs

         – Two 24-bit and one 16-bit Timer/Counters for Control (TCC), with extended functions:

   11. Up to four compare channels with optional complementary output

   12. Generation of synchronized pulse width modulation (PWM) pattern across port pins

   13. Deterministic fault protection, fast decay and configurable dead-time between complementary output

   14. Dithering that increase resolution with up to 5 bit and reduce quantization error

         – 32-bit Real Time Counter (RTC) with clock/calendar function

         – Watchdog Timer (WDT)

         – CRC-32 generator

         – One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface

    15. Embedded host and device function

    16. Eight endpoints

          – Up to six Serial Communication Interfaces (SERCOM) including one low-power SERCOM, each

    17. Temperature range

          – -40°C to 85°C

          – -40°C to 105°C

3. Performance level overview

    1. List of peripherals/clock sources not available in PL0:

        - USB (limited by logic frequency)

        - DFLL48M

    2. List of peripherals/clock sources with limited capabilities in PL0:

        - All AHB/APB peripherals are limited by CPU frequency

        - DPLL96M: may be able to generate 48MHz internally, but the output cannot be used by logic

        - GCLK: the maximum frequency is by factor 4 compared to PL2

        - SW interface: the maximum frequency is by factor 4 compared to PL2

        - TC: the maximum frequency is by factor 4 compared to PL2

        - TCC:the maximum frequency is by factor 4 compared to PL2

        - SERCOM: the maximum frequency is by factor 4 compared to PL2

    3. List of peripherals/clock sources with full capabilities in PL0:

        - AC

        - ADC

        - DAC

        - EIC

        - OPAMP

        - OSC16M

        - PTC

        - All 32KHz clock sources and peripherals