Allicdata Part #: | DS1100Z-35-ND |
Manufacturer Part#: |
DS1100Z-35 |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Maxim Integrated |
Short Description: | IC DELAY LINE 5TAP 35NS 8SOIC |
More Detail: | Delay Line IC Nonprogrammable 5 Tap 35ns 8-SOIC (0... |
DataSheet: | DS1100Z-35 Datasheet/PDF |
Quantity: | 1000 |
Series: | -- |
Packaging: | Tube |
Part Status: | Active |
Number of Taps/Steps: | 5 |
Function: | Nonprogrammable |
Delay to 1st Tap: | 7ns |
Tap Increment: | 7ns |
Available Total Delays: | 35ns |
Number of Independent Delays: | 1 |
Voltage - Supply: | 4.75 V ~ 5.25 V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 8-SOIC (0.154", 3.90mm Width) |
Supplier Device Package: | 8-SOIC |
Base Part Number: | DS1100 |
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Clock/Timing - Delay Lines
DS1100Z-35 is designed to delay an input signal by a period from 10 kHz to 10 MHz, depending on the model. This is accomplished by passing the input signal through a number of delay line stages, connected in series. Each stage gives the signal a delay time of one clock period, which can be set to a variety of different frequencies according to the model.
Application Field
This type of device has a variety of different applications, such as controlling the timing of digital logic circuits and providing matched delay between digital signals. It can also be used in test and measurement equipment, to precisely delay a signal so that it can be compared with other signals.
Working Principle
The DS1100Z-35 consists of a series of delay line stages, each preceded by an amplifier. The input signal is applied to the first amplifier, which amplifies it and sends it to the first delay line stage. This delay line stage consists of a pair of capacitors, one of which is charged during each half cycle of the clock signal. This clock signal is applied to both delay line stages and determines the overall delay time.
The amplified input signal is then applied to the terminal of the second capacitor of the first delay line stage, resulting in the delayed signal being generated at the other terminal. This signal is then sent to the next amplifier, which further amplifies it before sending it to the second delay line stage. This process is repeated until the desired delay time has been obtained. After the last delay line stage, the signal is sent to the output terminal.
The delay time of each stage can be adjusted by varying the frequency of the clock signal. Each delay line stage is tuned to a single frequency and so in order to delay the signal for a greater or smaller period, the frequency of the clock signal needs to be changed. This is usually done with a variable frequency oscillator (VFO) which can be adjusted to give the desired delay time.
Conclusion
The DS1100Z-35 is a versatile device capable of providing precise delays for a range of signal frequencies. The application fields for the device includes controlling the timing of digital logic circuits, providing matched delays, and providing a precise delay for signal comparisions in test and measurement equipment. The device is easy to use and configure with a variable frequency oscillator.
The specific data is subject to PDF, and the above content is for reference
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