SL15100ZC

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Clock Generators, PLLs, Frequency Synthesizers: SL15100ZC application field and working principle

The SL15100ZC is a clock generator, PLL, and frequency synthesizer that provides an integrated environment for frequency synthesizing and/or time base generation and clocking applications. It features low jitter, low phase noise, wide band divide-by-N capability, pin-programmable fractional-N/integer-N frequency synthesis, and a pull-in range of less than 4 kHz off the desired frequency. The device also allows the generation of output frequencies between 5 and 667 MHz.

The SL15100ZC contains a low-jitter, low-power pulse-swallow dual-modulus prescaler that can provide divide-by-2, 3, 4 ratio selections. The PLL includes an analog phase detector, an Analog-to-Digital Converter (ADC), and a low-noise charge pump with active gain regulation. The output drivers are optimized for nominal 50Ω resistive loads and can drive two outputs from 5 - 667 MHz.

The SL15100ZC is designed to be incorporated into a variety of communication/telecommunication, datacom, and multichannel transmissions systems such as Synchronous Digital Hierarchy (SDH), Synchronous Optical Network (SONET), fiber-optic modems, satellite receivers, microwave systems and wireless broadband access equipment. It can also be used in other initiatives and applications, including clock tree synthesis, jitter reduction, and clock multiplication.

The SL15100ZC features an integrated Fractional-N frequency synthesizer that provides a resolution of 0.1% across a frequency span of 5 – 667 MHz. Its pin-programmable pull-in range allows a frequency tuning of ±1 kHz or better in order to obtain precision time base generation or clock synthesis.

The SL15100ZC provides power management features such as SoftStart, power-down, stand-by period, and a low current-consumption Mode. The SoftStart feature allows the SL15100ZC to slowly ramp up its output frequency, preventing an instantaneous change in frequency and reducing the possibility of over-ranging the output buffer amplifiers. The power-down feature enables the user to save power by turning off the outputs when not in use. The Stand-by feature enables the SL15100ZC to operate without supplying clock inputs, reducing the need for external control circuitry. In addition, the low current-consumption Mode feature reduces the total system power consumption by reducing the output delays and eliminating unnecessary control circuit activities.

Overall, the SL15100ZC is a cost-effective solution for a wide variety of communication/telecommunication and datacom applications. With its excellent jitter and phase noise performance and wide range of features and functions, it is ideal for architects and designers who need to quickly and cost-effectively implement a reliable clock generation, PLL, and frequency synthesizing system.

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